Home
last modified time | relevance | path

Searched refs:RL (Results 1 - 20 of 20) sorted by relevance

/third_party/node/deps/v8/tools/release/
H A Dtest_scripts.py109 def RL(text, cb=None): function
307 RL("Y"),
319 RL("n"),
330 RL("Y"),
739 RL("Y"), # Automatically add corresponding ports (ab34567, ab56789)?
774 RL("Y"), # Automatically increment patch level?
776 RL("reviewer@chromium.org"), # V8 reviewer.
780 RL("LGTM"), # Enter LGTM for V8 CL.
876 RL("Y"), # Automatically add corresponding ports (ab34567, ab56789)?
912 RL("reviewe
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Remarks/
H A DYAMLRemarkSerializer.cpp24 Optional<RemarkLocation> RL, T FunctionName, in mapRemarkHeader()
29 io.mapOptional("DebugLoc", RL); in mapRemarkHeader()
77 static void mapping(IO &io, RemarkLocation &RL) { in mapping()
80 StringRef File = RL.SourceFilePath; in mapping()
81 unsigned Line = RL.SourceLine; in mapping()
82 unsigned Col = RL.SourceColumn; in mapping()
23 mapRemarkHeader(yaml::IO &io, T PassName, T RemarkName, Optional<RemarkLocation> RL, T FunctionName, Optional<uint64_t> Hotness, ArrayRef<Argument> Args) mapRemarkHeader() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.cpp75 void HexagonBlockRanges::RangeList::include(const RangeList &RL) { in include() argument
76 for (auto &R : RL) in include()
442 RangeList &RL = F->second; in computeDeadMap()
443 RangeList::iterator A = RL.begin(), Z = RL.end()-1; in computeDeadMap()
514 const HexagonBlockRanges::RangeList &RL) { in operator <<()
515 for (auto &R : RL) in operator <<()
532 const HexagonBlockRanges::RangeList &RL = I.second; in operator <<() local
533 OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n"; in operator <<()
513 operator <<(raw_ostream &OS, const HexagonBlockRanges::RangeList &RL) operator <<() argument
H A DHexagonBlockRanges.h114 void include(const RangeList &RL);
238 const HexagonBlockRanges::RangeList &RL);
H A DHexagonFrameLowering.cpp2188 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B]; in optimizeSpillSlots() local
2190 RL.add(LastStore[FI], LastLoad[FI], false, false); in optimizeSpillSlots()
2192 RL.add(IndexType::Entry, LastLoad[FI], false, false); in optimizeSpillSlots()
2205 auto &RL = FIRangeMap[I.first].Map[&B]; in optimizeSpillSlots() local
2208 RL.add(LS, LL, false, false); in optimizeSpillSlots()
2210 RL.add(IndexType::Entry, LL, false, false); in optimizeSpillSlots()
2217 auto &RL = FIRangeMap[I.first].Map[&B]; in optimizeSpillSlots() local
2218 RL.add(LS, IndexType::None, false, false); in optimizeSpillSlots()
2295 HexagonBlockRanges::RangeList &RL = FIRangeMap[FI].Map[&B]; in optimizeSpillSlots() local
2296 for (auto &Range : RL) { in optimizeSpillSlots()
[all...]
H A DHexagonGenInsert.cpp420 : RL(L), TRI(RI) {}
425 const OrderedRegisterList &RL;
431 OrderedRegisterList::const_iterator B = P.RL.begin(), E = P.RL.end();
H A DHexagonConstPropagation.cpp1863 bool evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs,
2517 bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, in evaluateHexRSEQ32() argument
2519 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg)); in evaluateHexRSEQ32()
2521 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH)) in evaluateHexRSEQ32()
H A DHexagonBitSimplify.cpp1699 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
1700 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, RL.Reg, RL.Sub, MRI);
/third_party/mbedtls/library/
H A DMakefile90 RL ?= ranlib macro
255 echo " RL $@"
256 $(RL) $(RLFLAGS) $@
284 echo " RL $@"
285 $(RL) $(RLFLAGS) $@
313 echo " RL $@"
314 $(RL) $(RLFLAGS) $@
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp379 auto RL = Reg2Local.find(Reg); in runOnMachineFunction() local
380 if (RL == Reg2Local.end() || RL->second < MFI.getParams().size()) in runOnMachineFunction()
383 MFI.setLocal(RL->second - MFI.getParams().size(), in runOnMachineFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp506 SDValue LL, LH, RL, RH, CL, CH; in SplitRes_SELECT() local
509 GetSplitOp(N->getOperand(2), RL, RH); in SplitRes_SELECT()
538 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL); in SplitRes_SELECT()
544 SDValue LL, LH, RL, RH; in SplitRes_SELECT_CC() local
547 GetSplitOp(N->getOperand(3), RL, RH); in SplitRes_SELECT_CC()
550 N->getOperand(1), LL, RL, N->getOperand(4)); in SplitRes_SELECT_CC()
H A DLegalizeIntegerTypes.cpp2910 SDValue LL, LH, RL, RH; in ExpandIntRes_Logical() local
2912 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_Logical()
2913 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); in ExpandIntRes_Logical()
2923 SDValue LL, LH, RL, RH; in ExpandIntRes_MUL() local
2925 GetExpandedInteger(N->getOperand(1), RL, RH); in ExpandIntRes_MUL()
2929 LL, LH, RL, RH)) in ExpandIntRes_MUL()
2953 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask); in ExpandIntRes_MUL()
2967 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift); in ExpandIntRes_MUL()
2987 DAG.getNode(ISD::MUL, dl, NVT, RL, LH))); in ExpandIntRes_MUL()
3070 SDValue LL, LH, RL, R in ExpandIntRes_MULFIX() local
[all...]
H A DTargetLowering.cpp5738 SDValue LH, SDValue RL, SDValue RH) const {
5759 // LL, LH, RL, and RH must be either all NULL or all set to a value.
5760 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
5761 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
5781 if (!LL.getNode() && !RL.getNode() &&
5784 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RHS);
5794 if (MakeMUL_LOHI(LL, RL, Lo, Hi, false)) {
5810 if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {
5839 if (!MakeMUL_LOHI(LL, RL, Lo, Hi, false))
5846 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
[all...]
H A DLegalizeVectorTypes.cpp1677 SDValue LL, LH, RL, RH; in SplitVecRes_SETCC() local
1686 GetSplitVector(N->getOperand(1), RL, RH); in SplitVecRes_SETCC()
1688 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1); in SplitVecRes_SETCC()
1690 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2)); in SplitVecRes_SETCC()
H A DDAGCombiner.cpp4522 /// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4525 SDValue LL, LR, RL, RR, N0CC, N1CC; in foldLogicOfSetCCs() local
4527 !isSetCCEquivalent(N1, RL, RR, N1CC)) in foldLogicOfSetCCs()
4533 RL.getValueType() == RR.getValueType() && in foldLogicOfSetCCs()
4544 if (OpVT != RL.getValueType()) in foldLogicOfSetCCs()
4568 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL); in foldLogicOfSetCCs()
4587 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL); in foldLogicOfSetCCs()
4595 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 && in foldLogicOfSetCCs()
4614 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR); in foldLogicOfSetCCs()
4626 if (LL == RL in foldLogicOfSetCCs()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ADT/
H A DImmutableSet.h516 TreeTy *RL = getLeft(R); in balanceTree() local
519 if (getHeight(RR) >= getHeight(RL)) in balanceTree()
520 return createNode(createNode(L,V,RL), R, RR); in balanceTree()
522 assert(!isEmpty(RL) && "RL cannot be empty because it has a height >= 1"); in balanceTree()
524 TreeTy *RLL = getLeft(RL); in balanceTree()
525 TreeTy *RLR = getRight(RL); in balanceTree()
527 return createNode(createNode(L,V,RLL), RL, createNode(RLR,R,RR)); in balanceTree()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp647 SDValue LL, RL, AddendL, AddendH; in TryExpandADDWithMul() local
650 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, in TryExpandADDWithMul()
664 AddendL, LL, RL); in TryExpandADDWithMul()
672 AddendL, LL, RL); in TryExpandADDWithMul()
683 AddendL, LL, RL); in TryExpandADDWithMul()
686 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); in TryExpandADDWithMul()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4054 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4061 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
4069 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4075 SDValue RL = SDValue(), SDValue RH = SDValue()) const;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3468 SDValue RL = Op.getOperand(1); in lowerSMUL_LOHI() local
3470 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63); in lowerSMUL_LOHI()
3475 LL, RL, Ops[1], Ops[0]); in lowerSMUL_LOHI()
3477 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL); in lowerSMUL_LOHI()
/third_party/alsa-lib/src/pcm/
H A Dpcm.c8368 _NAME(RL), _NAME(RR),

Completed in 103 milliseconds