| /third_party/libunwind/libunwind/src/x86_64/ |
| H A D | Gstep.c | 141 c->dwarf.loc[RIP] = DWARF_LOC (c->dwarf.cfa, 0); in unw_step()
174 * Check if previous RIP was invalid in unw_step()
182 Debug (2, "Previous RIP 0x%lx was invalid, attempting fixup\n", prev_ip); in unw_step()
186 /*Test to see if what we think is the previous RIP is valid*/ in unw_step()
201 * The call should have pushed RIP to the stack in unw_step()
203 * touched so RIP should be at RSP. in unw_step()
223 Debug (2, "RIP fixup didn't work, falling back\n"); in unw_step()
260 c->dwarf.loc[RIP] = rip_loc; in unw_step()
270 if (!DWARF_IS_NULL_LOC (c->dwarf.loc[RIP])) in unw_step()
272 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], in unw_step()
[all...] |
| H A D | init.h | 65 c->dwarf.loc[RIP] = REG_INIT_LOC(c, rip, RIP); in common_init()
67 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in common_init()
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| H A D | Gos-freebsd.c | 51 /* Check if RIP points at sigreturn sequence. in unw_is_signal_frame()
74 /* Check if RIP points at standard syscall sequence. in unw_is_signal_frame()
127 c->dwarf.loc[RIP] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RIP, 0); in x86_64_handle_signal_frame()
136 c->dwarf.loc[RIP] = DWARF_LOC (c->dwarf.cfa, 0); in x86_64_handle_signal_frame()
137 ret = dwarf_get (&c->dwarf, c->dwarf.loc[RIP], &c->dwarf.ip); in x86_64_handle_signal_frame()
138 Debug (1, "Frame Chain [RIP=0x%Lx] = 0x%Lx\n", in x86_64_handle_signal_frame()
139 (unsigned long long) DWARF_GET_LOC (c->dwarf.loc[RIP]), in x86_64_handle_signal_frame()
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| H A D | unwind_i.h | 55 #define RIP 16 macro
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| H A D | Gget_save_loc.c | 47 case UNW_X86_64_RIP: loc = c->dwarf.loc[RIP]; break; in unw_get_save_loc()
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| H A D | Gstash_frame.c | 97 /* Later we are going to fish out {RBP,RSP,RIP} from sigcontext via in tdep_stash_frame()
104 assert (DWARF_GET_LOC(d->loc[RIP]) - uc == UC_MCONTEXT_GREGS_RIP); in tdep_stash_frame()
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| H A D | Gregs.c | 77 c->dwarf.ip = *valp; /* also update the RIP cache */ in tdep_access_reg()
78 loc = c->dwarf.loc[RIP]; in tdep_access_reg()
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| H A D | Gos-solaris.c | 88 c->dwarf.loc[RIP] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RIP, 0); in x86_64_handle_signal_frame()
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| /third_party/skia/third_party/externals/swiftshader/third_party/marl/src/ |
| H A D | osfiber_asm_x64.h | 51 uintptr_t RIP; member
74 static_assert(offsetof(marl_fiber_context, RIP) == MARL_REG_RIP,
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| H A D | osfiber_x64.c | 35 ctx->RIP = (uintptr_t)&marl_fiber_trampoline; in marl_fiber_set_target()
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| /third_party/musl/arch/x32/bits/ |
| H A D | reg.h | 19 #define RIP 16 macro
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| /third_party/musl/arch/x86_64/bits/ |
| H A D | reg.h | 19 #define RIP 16 macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| H A D | RegionPrinter.cpp | 146 static RegionInfo *getGraph(RegionInfoPass *RIP) { in getGraph()
147 return &RIP->getRegionInfo(); in getGraph()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.cpp | 45 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
48 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
203 // NOSP does not contain RIP, so no special case here. in getPointerRegClass()
212 // NOSP does not contain RIP, so no special case here. in getPointerRegClass()
540 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP)) in getReservedRegs()
623 for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP}) in adjustStackMapLiveOutMask()
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| H A D | X86SpeculativeLoadHardening.cpp | 1119 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1159 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughIndirectBranches()
1717 // If we have at least one (non-frame-index, non-RIP) register operand, in tracePredStateThroughBlocksAndHarden()
1720 if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP && in tracePredStateThroughBlocksAndHarden()
1972 } else if (BaseMO.getReg() == X86::RIP || in hardenLoadAddr()
1974 // For both RIP-relative addressed loads or absolute loads, we cannot in hardenLoadAddr()
1984 << (BaseMO.getReg() == X86::RIP ? "RIP-relative" : "no-base") in hardenLoadAddr()
2503 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
2545 .addReg(/*Base*/ X86::RIP) in tracePredStateThroughCall()
[all...] |
| H A D | X86AsmPrinter.cpp | 292 BaseReg.getReg() == X86::RIP) in PrintLeaMemReference()
359 BaseReg.getReg() == X86::RIP) in PrintIntelMemReference()
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| H A D | X86ExpandPseudo.cpp | 93 .addReg(X86::RIP) in ExpandICallBranchFunnel()
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| /third_party/node/deps/v8/src/trap-handler/ |
| H A D | handler-inside-posix.cc | 126 auto* context_ip = CONTEXT_REG(rip, RIP); in TryHandleSignal()
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| /third_party/rust/crates/libc/src/fuchsia/ |
| H A D | x86_64.rs | 137 pub const RIP: ::c_int = 16; consts
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/ObjCARC/ |
| H A D | ObjCARCOpts.cpp | 1818 for (Instruction *RIP : NewRetainReleaseRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1819 if (ReleasesToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1822 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
1875 for (Instruction *RIP : NewReleaseRetainRRI.ReverseInsertPts) { in PairUpRetainsAndReleases()
1876 if (RetainsToMove.ReverseInsertPts.insert(RIP).second) { in PairUpRetainsAndReleases()
1879 const BBState &RIPBBState = BBStates[RIP->getParent()]; in PairUpRetainsAndReleases()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmParser.cpp | 1051 !(BaseReg == X86::RIP || BaseReg == X86::EIP || in CheckBaseRegAndIndexRegAndScale()
1071 if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) || in CheckBaseRegAndIndexRegAndScale()
1072 IndexReg == X86::EIP || IndexReg == X86::RIP || in CheckBaseRegAndIndexRegAndScale()
1122 // RIP/EIP-relative addressing is only supported in 64-bit mode. in CheckBaseRegAndIndexRegAndScale()
1124 (BaseReg == X86::RIP || BaseReg == X86::EIP)) { in CheckBaseRegAndIndexRegAndScale()
1171 if (RegNo == X86::RIZ || RegNo == X86::RIP || in ParseRegister()
1923 if (RegNo == X86::RIP) in ParseIntelOperand()
2063 if (Reg == X86::RIP) in ParseATTOperand()
2336 if (BaseReg == X86::RIP) in ParseMemOperand()
2339 if (IndexReg == X86::RIP) in ParseMemOperand()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 312 ? X86::RIP // Should have dwarf #16. in createX86MCRegisterInfo()
358 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; in createX86MCAsmInfo()
539 // RIP-relative addressing. in evaluateMemoryOperandAddress()
540 if (BaseReg.getReg() == X86::RIP) in evaluateMemoryOperandAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 410 ENTRY(RIP)
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| /third_party/libunwind/libunwind/src/ptrace/ |
| H A D | _UPT_reg_offset.c | 356 UNW_R_OFF(RIP, rip)
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| /third_party/rust/crates/libc/src/unix/linux_like/android/b64/x86_64/ |
| H A D | mod.rs | 752 pub const RIP: ::c_int = 16; consts
|