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Searched refs:REG (Results 1 - 25 of 25) sorted by relevance

/third_party/libunwind/libunwind/src/riscv/
H A Dsetcontext.S28 #define REG(X) (UC_MCONTEXT_REGS_OFF + SZREG * X)(a0) define
56 LOAD t1, REG(0)
57 LOAD ra, REG(1)
58 LOAD sp, REG(2)
59 LOAD s0, REG(8)
60 LOAD s1, REG(9)
61 LOAD a1, REG(11)
62 LOAD a2, REG(12)
63 LOAD a3, REG(13)
64 LOAD a4, REG(1
[all...]
H A Dgetcontext.S28 #define REG(X) (UC_MCONTEXT_REGS_OFF + SZREG * X)(a0) define
37 STORE ra, REG(0)
38 STORE ra, REG(1)
39 STORE sp, REG(2)
40 STORE s0, REG(8)
41 STORE s1, REG(9)
42 STORE x0, REG(10) /* Write 0 to a0 */
43 STORE a1, REG(11)
44 STORE a2, REG(12)
45 STORE a3, REG(1
[all...]
/third_party/elfutils/libcpu/
H A Dbpf_disasm.c55 #define REG(N) "r%" #N "$d" macro
56 #define REGU(N) "(u32)" REG(N)
57 #define REGS(N) "(s64)" REG(N)
65 #define A32(O, S) REG(1) " = " REGU(1) " " #O " " S
66 #define A64(O, S) REG(1) " " #O "= " S
68 #define LOAD(T) REG(1) " = *(" #T " *)(" REG(2) OFF(3) ")"
69 #define STORE(T, S) "*(" #T " *)(" REG(1) OFF(3) ") = " S
70 #define XADD(T, S) "lock *(" #T " *)(" REG(1) OFF(3) ") += " S
141 code_fmt = REG( in bpf_disasm()
[all...]
H A Driscv_disasm.c80 #define REG(nr) ((char *) regnames[nr]) macro
81 #define REGP(nr) REG (8 + (nr))
189 op[1] = REG (2); in riscv_disasm()
209 op[0] = op[1] = REG (rs1); in riscv_disasm()
216 op[0] = op[1] = REG (rs1); in riscv_disasm()
262 op[0] = op[1] = REG (reg); in riscv_disasm()
269 snprintf (addrbuf, sizeof (addrbuf), "%" PRIu64 "(%s)", opaddr, REG (2)); in riscv_disasm()
285 op[0] = REG((first >> 7) & 0x1f); in riscv_disasm()
303 op[0] = REG (rd); in riscv_disasm()
304 snprintf (addrbuf, sizeof (addrbuf), "%" PRIu16 "(%s)", uimm, REG ( in riscv_disasm()
[all...]
/third_party/mesa3d/src/freedreno/decode/
H A Dcffdec.c351 r = regbase("CP_SCRATCH[0].REG"); in reg_dump_scratch()
540 #define REG(x, fxn) { #x, fxn } macro
549 REG(CP_SCRATCH_REG0, reg_dump_scratch),
550 REG(CP_SCRATCH_REG1, reg_dump_scratch),
551 REG(CP_SCRATCH_REG2, reg_dump_scratch),
552 REG(CP_SCRATCH_REG3, reg_dump_scratch),
553 REG(CP_SCRATCH_REG4, reg_dump_scratch),
554 REG(CP_SCRATCH_REG5, reg_dump_scratch),
555 REG(CP_SCRATCH_REG6, reg_dump_scratch),
556 REG(CP_SCRATCH_REG
[all...]
/third_party/mesa3d/src/freedreno/perfcntrs/
H A Dfreedreno_perfcntr.h103 .select_reg = REG(_sel), .counter_reg_lo = REG(_lo), \
104 .counter_reg_hi = REG(_hi), \
108 .select_reg = REG(_sel), .counter_reg_lo = REG(_lo), \
109 .counter_reg_hi = REG(_hi), .enable = REG(_en), .clear = REG(_clr), \
H A Dfd5_perfcntr.c35 #define REG(_x) REG_A5XX_ ## _x macro
H A Dfd6_perfcntr.c36 #define REG(_x) REG_A6XX_ ## _x macro
H A Dfd2_perfcntr.c34 #define REG(_x) REG_A2XX_ ## _x macro
/third_party/optimized-routines/string/arm/
H A Dstrcpy.c16 #define magic1(REG) "#0x01010101"
17 #define magic2(REG) "#0x80808080"
19 #define magic1(REG) #REG
20 #define magic2(REG) #REG ", lsl #7"
/third_party/ltp/testcases/kernel/syscalls/nftw/
H A Dnftw.c73 REG, "byebye!\n"}, {
110 REG, "Do not eat yellow snow!\n"}, {
114 REG,
119 REG, "Do not eat yellow snow!\n"}, {
123 REG, ""}, {
127 REG, ""}, {
147 REG, ""}, {
171 REG, "left leaf\n"}, {
178 REG, "right leaf\n"}, {
H A Dnftw64.c73 REG, "byebye!\n"}, {
110 REG, "Do not eat yellow snow!\n"}, {
114 REG,
119 REG, "Do not eat yellow snow!\n"}, {
123 REG, ""}, {
127 REG, ""}, {
147 REG, ""}, {
171 REG, "left leaf\n"}, {
178 REG, "right leaf\n"}, {
H A Dnftw64.h61 #define REG 1 macro
H A Dnftw.h62 #define REG 1 macro
/third_party/node/deps/v8/src/trap-handler/
H A Dhandler-inside-posix.cc51 #define CONTEXT_REG(reg, REG) &uc->uc_mcontext.gregs[REG_##REG]
53 #define CONTEXT_REG(reg, REG) &uc->uc_mcontext->__ss.__##reg
55 #define CONTEXT_REG(reg, REG) &uc->uc_mcontext.mc_##reg
/third_party/skia/third_party/externals/libwebp/src/dsp/
H A Dneon.h85 #define PRINT_REG(REG, SIZE) do { \
87 printf("%s \t[%d]: 0x", #REG, SIZE); \
90 vst1_u8(_tmp, (REG)); \
94 vst1_u16(_tmp, (REG)); \
/third_party/libunwind/libunwind/src/tilegx/
H A Dgetcontext.S30 # define REG(X) LINUX_UC_MCONTEXT_GREGS + 8 * (X)
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64-inl.h239 #define DEFINE_FUNCTION(FN, REGTYPE, REG, OP) \
240 void TurboAssembler::FN(const REGTYPE REG, const MemOperand& addr) { \
242 LoadStoreMacro(REG, addr, OP); \
247 #define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \
248 void TurboAssembler::FN(const REGTYPE REG, const REGTYPE REG2, \
251 LoadStorePairMacro(REG, REG2, addr, OP); \
H A Dmacro-assembler-arm64.h783 #define DECLARE_FUNCTION(FN, REGTYPE, REG, OP) \
784 inline void FN(const REGTYPE REG, const MemOperand& addr);
1186 #define DECLARE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \
1187 inline void FN(const REGTYPE REG, const REGTYPE REG2, const MemOperand& addr);
/third_party/mesa3d/src/freedreno/.gitlab-ci/reference/
H A Dafuc_test.asm30 mov $02, 0x0883 ; CP_SCRATCH[0].REG
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc2069 #define DEFINE_FUNCTION(FN, REGTYPE, REG, OP) \ in Emit()
2070 void MacroAssembler::FN(const REGTYPE REG, const MemOperand& addr) { \ in Emit()
2072 LoadStoreMacro(REG, addr, OP); \ in Emit()
2119 #define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \ in Emit()
2120 void MacroAssembler::FN(const REGTYPE REG, \ in Emit()
2124 LoadStorePairMacro(REG, REG2, addr, OP); \ in Emit()
H A Dmacro-assembler-aarch64.h913 #define DECLARE_FUNCTION(FN, REGTYPE, REG, OP) \
914 void FN(const REGTYPE REG, const MemOperand& addr);
922 #define DECLARE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \
923 void FN(const REGTYPE REG, const REGTYPE REG2, const MemOperand& addr);
/third_party/lame/libmp3lame/i386/
H A Dnasm.h73 ;REG
/third_party/skia/src/core/
H A DSkVM.h113 enum { REG, MEM, LABEL } kind; enumerator
115 Operand(GP64 r) : reg (r), kind(REG ) {} in Operand()
116 Operand(Xmm r) : reg (r), kind(REG ) {} in Operand()
117 Operand(Ymm r) : reg (r), kind(REG ) {} in Operand()
H A DSkVM.cpp1943 if (dst.kind == Operand::REG) {
2169 case Operand::REG: {

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