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Searched refs:RD (Results 1 - 25 of 46) sorted by relevance

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/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeRISCV_64.c34 return push_inst(compiler, ADDI | RD(dst_r) | RS1(TMP_ZERO) | IMM_I(imm)); in load_immediate()
39 FAIL_IF(push_inst(compiler, LUI | RD(dst_r) | (sljit_ins)0x80000000u)); in load_immediate()
40 return push_inst(compiler, XORI | RD(dst_r) | RS1(dst_r) | IMM_I(imm)); in load_immediate()
46 FAIL_IF(push_inst(compiler, LUI | RD(dst_r) | (sljit_ins)(imm & ~0xfff))); in load_immediate()
51 return push_inst(compiler, ADDI | RD(dst_r) | RS1(dst_r) | IMM_I(imm)); in load_immediate()
64 FAIL_IF(push_inst(compiler, LUI | RD(dst_r) | (sljit_ins)0x80000000u)); in load_immediate()
65 FAIL_IF(push_inst(compiler, XORI | RD(dst_r) | RS1(dst_r) | IMM_I(high))); in load_immediate()
70 FAIL_IF(push_inst(compiler, LUI | RD(dst_r) | (sljit_ins)(high & ~0xfff))); in load_immediate()
73 FAIL_IF(push_inst(compiler, ADDI | RD(dst_r) | RS1(dst_r) | IMM_I(high))); in load_immediate()
76 FAIL_IF(push_inst(compiler, SLLI | RD(dst_ in load_immediate()
[all...]
H A DsljitNativeRISCV_common.c65 #define RD(rd) ((sljit_ins)reg_map[rd] << 7) macro
317 inst[0] = LUI | RD(reg) | (sljit_ins)((sljit_sw)addr & ~0xfff); in load_addr_to_reg()
322 inst[0] = LUI | RD(reg) | (sljit_ins)((sljit_sw)addr & ~0xfff); in load_addr_to_reg()
329 inst[0] = LUI | RD(reg) | (sljit_ins)0x80000000u; in load_addr_to_reg()
330 inst[1] = XORI | RD(reg) | RS1(reg) | IMM_I(high); in load_addr_to_reg()
335 inst[0] = LUI | RD(reg) | (sljit_ins)(high & ~0xfff); in load_addr_to_reg()
336 inst[1] = ADDI | RD(reg) | RS1(reg) | IMM_I(high); in load_addr_to_reg()
339 inst[2] = SLLI | RD(reg) | RS1(reg) | IMM_I(12); in load_addr_to_reg()
352 inst[0] = LUI | RD(TMP_REG3) | (sljit_ins)(high << 12); in load_addr_to_reg()
354 inst[0] = LUI | RD(TMP_REG in load_addr_to_reg()
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H A DsljitNativeARM_64.c55 #define RD(rd) ((sljit_ins)reg_map[rd]) macro
155 FAIL_IF(push_inst(compiler, MOVZ | RD(dst) | ((sljit_ins)(imm & 0xffff) << 5))); in emit_imm64_const()
156 FAIL_IF(push_inst(compiler, MOVK | RD(dst) | (((sljit_ins)(imm >> 16) & 0xffff) << 5) | (1 << 21))); in emit_imm64_const()
157 FAIL_IF(push_inst(compiler, MOVK | RD(dst) | (((sljit_ins)(imm >> 32) & 0xffff) << 5) | (2 << 21))); in emit_imm64_const()
158 return push_inst(compiler, MOVK | RD(dst) | ((sljit_ins)(imm >> 48) << 5) | (3 << 21)); in emit_imm64_const()
515 return push_inst(compiler, MOVZ | RD(dst) | ((sljit_ins)imm << 5)); in load_immediate()
518 return push_inst(compiler, MOVN | RD(dst) | (((sljit_ins)~imm & 0xffff) << 5)); in load_immediate()
522 return push_inst(compiler, MOVZ | RD(dst) | ((sljit_ins)(imm >> 16) << 5) | (1 << 21)); in load_immediate()
524 return push_inst(compiler, (MOVN ^ W_OP) | RD(dst) | (((sljit_ins)~imm & 0xffff) << 5)); in load_immediate()
526 return push_inst(compiler, (MOVN ^ W_OP) | RD(ds in load_immediate()
[all...]
H A DsljitNativeARM_32.c73 #define RD(rd) ((sljit_uw)reg_map[rd] << 12) macro
411 FAIL_IF(push_inst(compiler, MOVW | RD(reg) | ((imm << 4) & 0xf0000) | ((sljit_u32)imm & 0xfff))); in emit_imm()
412 return push_inst(compiler, MOVT | RD(reg) | ((imm >> 12) & 0xf0000) | (((sljit_u32)imm >> 16) & 0xfff)); in emit_imm()
480 sljit_s32 bl = (mov_pc & 0x0000f000) != RD(TMP_PC); in inline_set_jump_addr()
1025 (data_transfer_insts[(type) & 0xf] | ((add) << 23) | RD(target_reg) | RN(base_reg) | (sljit_uw)(arg))
1095 FAIL_IF(push_inst(compiler, 0xe52d0004 | RD(TMP_REG2))); in sljit_emit_enter()
1102 FAIL_IF(push_inst(compiler, SUB | RD(SLJIT_SP) | RN(SLJIT_SP) | SRC2_IMM | sizeof(sljit_sw))); in sljit_emit_enter()
1165 FAIL_IF(push_inst(compiler, MOV | RD(tmp) | (offset >> 2))); in sljit_emit_enter()
1167 FAIL_IF(push_inst(compiler, LDR | 0x800000 | RN(SLJIT_SP) | RD(tmp) | (offset + (sljit_uw)size - 4 * sizeof(sljit_sw)))); in sljit_emit_enter()
1203 FAIL_IF(push_inst(compiler, MOV | RD(SLJIT_S in sljit_emit_enter()
[all...]
H A DsljitNativeRISCV_32.c33 return push_inst(compiler, ADDI | RD(dst_r) | RS1(TMP_ZERO) | IMM_I(imm)); in load_immediate()
38 FAIL_IF(push_inst(compiler, LUI | RD(dst_r) | (sljit_ins)(imm & ~0xfff))); in load_immediate()
43 return push_inst(compiler, ADDI | RD(dst_r) | RS1(dst_r) | IMM_I(imm)); in load_immediate()
51 FAIL_IF(push_inst(compiler, LUI | RD(dst) | (sljit_ins)(init_value & ~0xfff))); in emit_const()
/third_party/skia/third_party/externals/spirv-tools/test/
H A Dhex_float_test.cpp773 using RD = round_direction;
798 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToZero},
799 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToNearestEven},
800 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToPositiveInfinity},
801 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToNegativeInfinity},
802 {float_fractions({0, 1}), std::make_pair(half_bits_set({0}), false), RD::kToZero},
804 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD::kToZero},
805 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0, 9}), false), RD::kToPositiveInfinity},
806 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD::kToNegativeInfinity},
807 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/test/
H A Dhex_float_test.cpp773 using RD = round_direction;
798 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToZero},
799 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToNearestEven},
800 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToPositiveInfinity},
801 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToNegativeInfinity},
802 {float_fractions({0, 1}), std::make_pair(half_bits_set({0}), false), RD::kToZero},
804 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD::kToZero},
805 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0, 9}), false), RD::kToPositiveInfinity},
806 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD::kToNegativeInfinity},
807 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD
[all...]
/third_party/spirv-tools/test/
H A Dhex_float_test.cpp773 using RD = round_direction;
798 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToZero},
799 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToNearestEven},
800 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToPositiveInfinity},
801 {float_fractions({0}), std::make_pair(half_bits_set({}), false), RD::kToNegativeInfinity},
802 {float_fractions({0, 1}), std::make_pair(half_bits_set({0}), false), RD::kToZero},
804 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD::kToZero},
805 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0, 9}), false), RD::kToPositiveInfinity},
806 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD::kToNegativeInfinity},
807 {float_fractions({0, 1, 11}), std::make_pair(half_bits_set({0}), false), RD
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/
H A DLoopUtils.cpp881 using RD = RecurrenceDescriptor; in createSimpleTargetReduction()
882 RD::MinMaxRecurrenceKind MinMaxKind = RD::MRK_Invalid; in createSimpleTargetReduction()
916 MinMaxKind = Flags.IsSigned ? RD::MRK_SIntMax : RD::MRK_UIntMax; in createSimpleTargetReduction()
921 MinMaxKind = Flags.IsSigned ? RD::MRK_SIntMin : RD::MRK_UIntMin; in createSimpleTargetReduction()
929 MinMaxKind = RD::MRK_FloatMax; in createSimpleTargetReduction()
932 MinMaxKind = RD::MRK_FloatMin; in createSimpleTargetReduction()
951 using RD in createTargetReduction()
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H A DSymbolRewriter.cpp125 static bool classof(const RewriteDescriptor *RD) { in classof() argument
126 return RD->getType() == DT; in classof()
166 static bool classof(const RewriteDescriptor *RD) { in classof() argument
167 return RD->getType() == DT; in classof()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp228 static bool isTransparentCopy(const BitTracker::RegisterRef &RD,
922 // Check if RD could be replaced with RS at any possible use of RD.
926 bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD,
928 if (!Register::isVirtualRegister(RD.Reg) ||
932 auto *DRC = getFinalVRegClass(RD, MRI);
1066 bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
1275 // Calculates the used bits in RD ("defined register"), and checks if these
1276 // bits in RS ("used register") and RD are identical.
1277 bool RedundantInstrElimination::usedBitsEqual(BitTracker::RegisterRef RD,
[all...]
H A DBitTracker.cpp726 RegisterRef RD = MI.getOperand(0);
727 assert(RD.Sub == 0);
734 uint16_t W = getRegBitWidth(RD);
736 Res.insert(RegisterCell::ref(getCell(RS, Inputs)), mask(RD.Reg, SS));
737 Res.insert(RegisterCell::ref(getCell(RT, Inputs)), mask(RD.Reg, ST));
738 putCell(RD, Res, Outputs);
745 RegisterRef RD = MI.getOperand(0);
747 assert(RD.Sub == 0);
748 uint16_t WD = getRegBitWidth(RD);
755 putCell(RD, Re
[all...]
H A DHexagonExpandCondsets.cpp220 MachineInstr *getReachingDefForPred(RegisterRef RD,
742 /// Find the reaching definition for a predicated use of RD. The RD is used
744 /// definitions that set RD under the opposite conditions.
745 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD, in getReachingDefForPred() argument
763 // Check the defs. If the PredR is defined, invalidate it. If RD is in getReachingDefForPred()
773 if (RR.Reg != RD.Reg) in getReachingDefForPred()
778 if (RR.Sub == RD.Sub) in getReachingDefForPred()
780 if (RR.Sub == 0 || RD.Sub == 0) in getReachingDefForPred()
1021 // RD in predicate()
1202 RegisterRef RD = CI->getOperand(0); coalesceSegments() local
[all...]
H A DRDFGraph.cpp447 Ref.RD = DA.Id; in linkToDef()
454 Ref.RD = DA.Id; in linkToDef()
1546 if (NodeId RD = RA.Addr->getReachingDef()) { in removeUnusedPhis()
1547 auto RDA = addr<DefNode*>(RD); in removeUnusedPhis()
1722 NodeId RD = UA.Addr->getReachingDef(); in unlinkUseDF() local
1725 if (RD == 0) { in unlinkUseDF()
1730 auto RDA = addr<DefNode*>(RD); in unlinkUseDF()
1750 // RD in unlinkDefDF()
1767 NodeId RD = DA.Addr->getReachingDef(); in unlinkDefDF() local
1770 // Also, defs reached by DA are now "promoted" to being reached by RD, in unlinkDefDF()
[all...]
H A DRDFCopy.cpp95 if (NodeId RD = RA.Addr->getReachingDef()) in getLocalReachingDef()
96 return RD; in getLocalReachingDef()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp115 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
120 SETHIInst.addOperand(RD); in EmitSETHI()
126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
131 Inst.addOperand(RD); in EmitBinary()
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
140 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI); in EmitOR()
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
146 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI); in EmitADD()
150 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitSHL()
152 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, ST in EmitSHL()
114 EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) EmitSETHI() argument
125 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) EmitBinary() argument
137 EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) EmitOR() argument
143 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) EmitADD() argument
149 EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) EmitSHL() argument
156 EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI) EmitHiLo() argument
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp898 bool hasSameData(ReductionData &RD) const { in hasSameData()
899 return Kind == RD.Kind && Opcode == RD.Opcode; in hasSameData()
941 Optional<ReductionData> RD = getReductionData(I); in matchPairwiseReductionAtLevel() local
942 if (!RD) in matchPairwiseReductionAtLevel()
945 ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS); in matchPairwiseReductionAtLevel()
948 ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS); in matchPairwiseReductionAtLevel()
973 if (NextLevelOpL && NextLevelOpL != RD->RHS) in matchPairwiseReductionAtLevel()
975 else if (NextLevelOpR && NextLevelOpR != RD->LHS) in matchPairwiseReductionAtLevel()
978 NextLevelOp = NextLevelOpL ? RD in matchPairwiseReductionAtLevel()
[all...]
/third_party/musl/libc-test/src/math/
H A Dfenv.c192 T(RD, 0x1p+0, 0x1p-52, 0x1.0000000000001p+0, 0x0p+0, 0)
193 T(RD, 0x1p+0, 0x1p-53, 0x1p+0, -0x1p-1, INEXACT)
194 T(RD, 0x1p+0, 0x1.01p-53, 0x1p+0, -0x1.01p-1, INEXACT)
195 T(RD, 0x1p+0, -0x1p-54, 0x1.fffffffffffffp-1, -0x1p-1, INEXACT)
196 T(RD, 0x1p+0, -0x1.01p-54, 0x1.fffffffffffffp-1, -0x1.fep-2, INEXACT)
197 T(RD, -0x1p+0, -0x1p-53, -0x1.0000000000001p+0, -0x1p-1, INEXACT)
198 T(RD, -0x1p+0, -0x1.01p-53, -0x1.0000000000001p+0, -0x1.fep-2, INEXACT)
199 T(RD, -0x1p+0, 0x1p-54, -0x1p+0, -0x1p-2, INEXACT)
200 T(RD, -0x1p+0, 0x1.01p-54, -0x1p+0, -0x1.01p-2, INEXACT)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/
H A DInstrBuilder.cpp633 for (const ReadDescriptor &RD : D.Reads) {
634 if (!RD.isImplicitRead()) {
636 const MCOperand &Op = MCI.getOperand(RD.OpIndex);
643 RegID = RD.RegisterID;
651 NewIS->getUses().emplace_back(RD, RegID);
658 if (!RD.isImplicitRead())
666 if (Mask.getBitWidth() > RD.UseIndex) {
667 // Okay. This map describe register use `RD.UseIndex`.
668 if (Mask[RD.UseIndex])
/third_party/musl/libc-test/src/math/gen/
H A Dgen.h7 #undef RD macro
11 #define RD FE_DOWNWARD macro
H A Dutil.c145 case RD: return "RD"; in rstr()
156 else if (strcmp(s, "RD") == 0) in rconv()
157 *r = RD; in rconv()
/third_party/skia/third_party/externals/harfbuzz/src/
H A Dhb-ot-shape-complex-thai.cc94 RD /* Remove descender from base */ enumerator
150 case RD: pua_mappings = RD_mappings; break; in thai_pua_shape()
215 /*B1*/ {{NOP,B1}, {RD, B2}, {NOP, B1}},
256 if (action == RD) in do_thai_pua_shaping()
/third_party/musl/libc-test/src/common/
H A Dmtest.h7 #undef RD macro
20 #define RD FE_DOWNWARD macro
22 #define RD -1 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/
H A DInstruction.h228 const ReadDescriptor *RD; member in llvm::mca::ReadState
258 : RD(&Desc), RegisterID(RegID), PRFID(0), DependentWrites(0), in ReadState()
262 const ReadDescriptor &getDescriptor() const { return *RD; } in getDescriptor()
263 unsigned getSchedClass() const { return RD->SchedClassID; } in getSchedClass()
270 bool isImplicitRead() const { return RD->isImplicitRead(); } in isImplicitRead()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp327 /// \returns true if is legal to reassign this closure to domain \p RD.
328 bool isLegal(RegDomain RD) const { return LegalDstDomains[RD]; } in isLegal()
330 /// Mark this closure as illegal for reassignment to domain \p RD.
331 void setIllegal(RegDomain RD) { LegalDstDomains[RD] = false; } in setIllegal() argument
445 RegDomain RD = getDomain(MRI->getRegClass(Reg), MRI->getTargetRegisterInfo()); in visitRegister()
448 Domain = RD; in visitRegister()
450 if (Domain != RD) in visitRegister()

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