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Searched refs:RAX (Results 1 - 25 of 26) sorted by relevance

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/third_party/libunwind/libunwind/src/x86_64/
H A Dinit.h49 c->dwarf.loc[RAX] = REG_INIT_LOC(c, rax, RAX); in common_init()
H A Dunwind_i.h39 #define RAX 0 macro
H A DGregs.c104 loc = c->dwarf.loc[(reg == UNW_X86_64_RAX) ? RAX : RDX]; in tdep_access_reg()
H A DGos-solaris.c72 c->dwarf.loc[RAX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RAX, 0); in x86_64_handle_signal_frame()
H A DGos-freebsd.c111 c->dwarf.loc[RAX] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RAX, 0); in x86_64_handle_signal_frame()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86WinAllocaExpander.cpp219 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower()
233 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower()
246 // The probe lowering expects the amount in RAX/EAX. in lower()
247 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower()
H A DX86FrameLowering.cpp200 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX || in isEAXLiveIn()
264 unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX); in emitSPUpdate()
285 // frame), it's worth spilling RAX to materialize this immediate. in emitSPUpdate()
308 // Exchange the new SP in RAX with the top of the stack. in emitSPUpdate()
325 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) in emitSPUpdate()
536 // RAX contains the number of bytes of desired stack adjustment.
545 // SizeReg = RAX;
560 // RSP = RSP - RAX
584 // registers. For the prolog expansion we use RAX, RCX and RDX.
587 const Register SizeReg = InProlog ? X86::RAX
[all...]
H A DX86SelectionDAGInfo.cpp56 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, in EmitTargetCodeForMemset()
127 ValReg = X86::RAX; in EmitTargetCodeForMemset()
H A DX86MCInstLower.cpp303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
330 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
364 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortMoveForm()
741 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX; in Lower()
1064 BaseReg = X86::RAX; in EmitNop()
1091 IndexReg = X86::RAX; in EmitNop()
1097 IndexReg = X86::RAX; in EmitNop()
1108 IndexReg = X86::RAX; in EmitNop()
1114 IndexReg = X86::RAX; in EmitNop()
1120 IndexReg = X86::RAX; in EmitNop()
[all...]
H A DX86InstructionSelector.cpp1596 X86::RAX, in selectDivRem()
1599 {X86::IDIV64r, X86::CQO, Copy, X86::RAX, S}, // SDiv in selectDivRem()
1601 {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv in selectDivRem()
H A DX86FastISel.cpp1270 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet()
1901 { &X86::GR64RegClass, X86::RAX, X86::RDX, { in X86SelectDivRem()
1902 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv in X86SelectDivRem()
1904 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv in X86SelectDivRem()
2948 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX }; in fastLowerIntrinsicCall()
2949 // First copy the first operand into RAX, which is an implicit input to in fastLowerIntrinsicCall()
H A DX86ISelDAGToDAG.cpp4456 unsigned PtrReg = Use64BitPtr ? X86::RAX : X86::EAX; in Select()
4715 LoReg = X86::RAX; in Select()
4799 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
4903 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
H A DX86ISelLowering.cpp2724 // which is returned in RAX / RDX. in LowerReturn()
2803 X86::RAX : X86::EAX; in LowerReturn()
2807 // RAX/EAX now acts like a return value. in LowerReturn()
18236 X86::RAX, X86II::MO_TLSGD);
18252 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
18405 unsigned Reg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
24676 LO = DAG.getCopyFromReg(Chain, DL, X86::RAX, MVT::i64, SDValue(N1, 1));
25152 return Subtarget.isTarget64BitLP64() ? X86::RAX : X86::EAX;
[all...]
/third_party/musl/arch/x32/bits/
H A Dreg.h13 #define RAX 10 macro
/third_party/musl/arch/x86_64/bits/
H A Dreg.h13 #define RAX 10 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp156 {codeview::RegisterId::RAX, X86::RAX}, in initLLVMToSEHAndCVRegMapping()
615 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
627 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
664 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
700 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
736 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: in getX86SubSuperRegisterOrZero()
737 return X86::RAX; in getX86SubSuperRegisterOrZero()
/third_party/lzma/Asm/x86/
H A D7zAsm.asm18 ifdef RAX
129 r0 equ RAX
/third_party/node/deps/v8/src/trap-handler/
H A Dhandler-inside-posix.cc147 auto* return_reg = CONTEXT_REG(rax, RAX); in TryHandleSignal()
/third_party/rust/crates/libc/src/fuchsia/
H A Dx86_64.rs131 pub const RAX: ::c_int = 10; consts
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h173 ENTRY(RAX) \
191 ENTRY(RAX) \
/third_party/libunwind/libunwind/tests/
H A Dx64-test-dwarf-expressions.S32 # RAX flows back unchanged. Adding any function calls to the below may clobber
/third_party/libunwind/libunwind/src/ptrace/
H A D_UPT_reg_offset.c340 UNW_R_OFF(RAX, rax)
/third_party/rust/crates/libc/src/unix/linux_like/android/b64/x86_64/
H A Dmod.rs746 pub const RAX: ::c_int = 10; consts
/third_party/rust/crates/libc/src/unix/linux_like/linux/gnu/b64/x86_64/
H A Dmod.rs761 pub const RAX: ::c_int = 10; consts
/third_party/rust/crates/libc/src/unix/linux_like/linux/musl/b64/x86_64/
H A Dmod.rs623 pub const RAX: ::c_int = 10; consts

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