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Searched refs:R7 (Results 1 - 25 of 39) sorted by relevance

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/third_party/libunwind/libunwind/src/arm/
H A DGstash_frame.c43 rs->reg.where[R7], rs->reg.val[R7], DWARF_GET_LOC(d->loc[R7]), in tdep_stash_frame()
48 - CFA is register-relative offset off R7 or SP; in tdep_stash_frame()
50 - R7 is unsaved or saved at CFA+offset, offset != -1; in tdep_stash_frame()
55 && (rs->reg.val[DWARF_CFA_REG_COLUMN] == R7 in tdep_stash_frame()
59 && (rs->reg.where[R7] == DWARF_WHERE_UNDEF in tdep_stash_frame()
60 || rs->reg.where[R7] == DWARF_WHERE_SAME in tdep_stash_frame()
61 || (rs->reg.where[R7] == DWARF_WHERE_CFAREL in tdep_stash_frame()
62 && labs(rs->reg.val[R7]) < ( in tdep_stash_frame()
[all...]
H A Dunwind_i.h35 #define R7 7 macro
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
H A Dcomc597.mme.h155 MME_INSN(0, MERGE, R7, ZERO, R1, (1<<10)|(5<<5)|0, ALU1, NONE,
159 MME_INSN(1, ADD, ZERO, R7, IMMED, (1<<12)|0x0600/4, ALU0, ALU1,
202 OR, R7, R1, R2, 0, NONE, NONE),
205 MME_INSN(0, AND, R7, R7, IMMED, 1, NONE, NONE,
207 MME_INSN(0, BEQ, ZERO, R7, ZERO, (2<<14)|0x0002, NONE, NONE,
215 MME_INSN(0, OR, R7, R3, R4, 0, NONE, NONE,
217 MME_INSN(0, AND, R7, R7, IMMED, 1, NONE, NONE,
219 MME_INSN(0, BEQ, ZERO, R7, ZER
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp42 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
47 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
58 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
/third_party/ffmpeg/libavcodec/arm/
H A Dsimple_idct_arm.S81 mov r7, r1, asr #16 @ R7=R1>>16=ROWr16[1] (evaluate it now, as it could be useful later)
83 orrs r5, r5, r7 @ R5=R4 | R3 | R2 | R7
88 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
108 mul r7, r11, r7 @ R7=W7*ROWr16[1]=b3 (ROWr16[1] must be the second arg, to have the possibility to save 1 cycle)
116 mlane r7, r10, r2, r7 @ R7-=W5*ROWr16[3]=b3 (ROWr16[3] must be the second arg, to have the possibility to save 1 cycle)
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
144 mlane r7, r9, r3, r7 @ R7+=W3*ROWr16[5]=b3
146 mlane r1, r8, r3, r1 @ R7-=W1*ROWr16[5]=b1
153 mlane r7, r8, r4, r7 @ R7
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
/third_party/ffmpeg/libswscale/x86/
H A Dyuv_2_rgb.asm197 paddsw m5, m1 ; R1 R3 R5 R7 ...
205 packuswb m0, m3 ; R0 R2 R4 R6 ... R1 R3 R5 R7 ...
212 punpcklbw m6, m_red ; B0 R1 B2 R3 B4 R5 B6 R7 B8 R9 ...
217 punpckhwd m5, m6 ; R4 G4 B4 R5 R6 G6 B6 R7
224 pand m7, [mask_0110] ; -- -- R6 G6 B6 R7 -- --
250 movd [imageq + 18], m5 ; R6 G6 B6 R7
285 punpckhbw m1, m3 ; R0 R1 R2 R3 ... R7
H A Dinput.asm175 pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
187 movd m6, [srcq+20] ; (byte) { R6, B7, G7, R7 }
189 punpckldq m3, m6 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
193 punpcklbw m3, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
199 pmaddwd m3, coeff2 ; (dword) { R4*RY, G5+GY + R5*RY, R6*RY, G7+GY + R7*RY }
285 pshufb m5, m4, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
289 movd m3, [srcq+20] ; (byte) { R6, B7, G7, R7 }
291 punpckldq m5, m3 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
293 punpcklbw m5, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
297 pmaddwd m3, m5, coeffU2 ; (dword) { R4*BU, G5*GU + R5*BU, R6*BU, G7*GU + R7*B
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBPFFrameLowering.cpp36 SavedRegs.reset(BPF::R7); in determineCalleeSaves()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h59 case Lanai::R7: in getLanaiRegisterNumbering()
/third_party/ffmpeg/libavcodec/x86/
H A Dvp3dsp.asm281 psubsw m7, m0 ; r7 = R7 = G. - C.
315 psubsw m7, m0 ; r7 = R7 = G. - C.
316 paddsw m7, OC_8 ; adjust R7 (and R0) for shift
371 punpckhdq m6, m0 ; r6 = h3 g3 f3 e3 = R7
491 psubsw m7, m0 ; xmm7 = G. - C. = R7
492 ADD(m7) ; Adjust R7 and R0 before shifting
H A Dsimple_idct.asm87 movq mm3, [blockq + %4] ; R7 R5 r7 r5
176 movq mm3, [blockq + %4] ; R7 R5 r7 r5
253 movq mm3, %4 ; R7 R5 r7 r5
327 movq mm3, %4 ; R7 R5 r7 r5
389 movq mm3, %4 ; R7 R5 r7 r5
444 movq mm3, %4 ; R7 R5 r7 r5
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp222 case ARM::R7: in emitPrologue()
287 case ARM::R7: in emitPrologue()
679 // R7 may be used as a frame pointer, hence marked as not generally in emitPopSpecialFixUp()
683 PopFriendly.set(ARM::R7); in emitPopSpecialFixUp()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
985 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
H A DARMBaseRegisterInfo.h48 case R4: case R5: case R6: case R7: in isARMArea1Register()
H A DARMFrameLowering.cpp436 case ARM::R7: in emitPrologue()
589 // For iOS, FP is R7, which has now been stored in spill area 1. in emitPrologue()
643 case ARM::R7: in emitPrologue()
1735 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. in determineCalleeSaves()
1743 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1759 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1891 if (FramePtr == ARM::R7) in determineCalleeSaves()
1962 if (SavedRegs.test(ARM::R7)) { in determineCalleeSaves()
1967 AvailableRegs.push_back(ARM::R7); in determineCalleeSaves()
2028 // If LR is not spilled, but at least one of R4, R5, R6, and R7 i in determineCalleeSaves()
[all...]
/third_party/ltp/testcases/kernel/syscalls/ptrace/
H A Dptrace04.c34 R(R0) R(R1) R(R2) R(R3) R(R4) R(R5) R(R6) R(R7)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp214 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
219 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/third_party/ltp/tools/sparse/sparse-src/validation/
H A Drepeat.h8 #define R7(P, S) R6(P,S##0) R6(P,S##1) macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h164 case R4: case R5: case R6: case R7: in isARMLowRegister()
H A DARMAsmBackend.cpp1160 if (CFARegister != ARM::R7) { in generateCompactUnwindEncoding()
1176 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) { in generateCompactUnwindEncoding()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp157 Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp115 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 in getCallerSavedRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp86 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,

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