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Searched refs:R6 (Results 1 - 25 of 37) sorted by relevance

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/third_party/ltp/tools/sparse/sparse-src/validation/
H A Drepeat.h7 #define R6(P, S) R3(P,S##0) R3(P,S##1) R3(P,S##2) R3(P,S##3) R3(P,S##4) R3(P,S##5) R3(P,S##6) R3(P,S##7) macro
8 #define R7(P, S) R6(P,S##0) R6(P,S##1)
9 #define R8(P, S) R6(P,S##0) R6(P,S##1) R6(P,S##2) R6(P,S##3)
10 #define R9(P, S) R6(P,S##0) R6(P,S##1) R6(
[all...]
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
H A Dcomc597.mme.h154 MERGE, R6, ZERO, R1, (2<<10)|(5<<5)|0, NONE, NONE),
156 ADD, ZERO, R6, IMMED, (1<<12)|0x1c04/4, NONE, NONE),
204 ADD, R6, IMMED, ZERO, 0x60, NONE, NONE),
210 MME_INSN(0, ADD, R6, IMMED, ZERO, 0x200, NONE, NONE,
222 MME_INSN(0, ADD, R6, ZERO, ZERO, 0, NONE, NONE,
228 MME_INSN(0, ADD, ZERO, R6, ZERO, 0, NONE, ALU0,
248 ADD, R6, IMMED, ZERO, 0x60, NONE, NONE),
254 MME_INSN(0, ADD, R6, IMMED, ZERO, 0x200, NONE, NONE,
266 MME_INSN(0, ADD, R6, ZERO, ZERO, 0, NONE, NONE,
272 MME_INSN(0, ADD, ZERO, R6, ZER
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.cpp42 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
47 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
52 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
58 MSP430::R5, MSP430::R6, MSP430::R7, in getCalleeSavedRegs()
/third_party/ffmpeg/libavcodec/arm/
H A Dsimple_idct_arm.S82 ldrsh r6, [r14, #0] @ R6=ROWr16[0]
88 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
159 @@ R5=b2, R6=ROWr16[0], R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
169 mul r6, r9, r6 @ R6=W4*ROWr16[0]
172 add r6, r6, #ROW_SHIFTED_1 @ R6=W4*ROWr16[0] + 1<<(ROW_SHIFT-1) (a0)
185 add r6, r6, r11 @ R6=a0+W2*ROWr16[2] (a0)
189 @@ R5=b2, R6=a0, R7=b3, R8=W2, R9=W4, R10=W6, R11 (free),
204 addne r6, r6, r11 @ R6
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
/third_party/ffmpeg/libswscale/x86/
H A Dinput.asm175 pshufb m3, m2, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
176 pshufb m2, shuf_rgb1 ; (word) { B4, G4, R4, B5, B6, G6, R6, B7 }
186 movd m5, [srcq+18] ; (byte) { B6, G6, R6, B7 }
187 movd m6, [srcq+20] ; (byte) { R6, B7, G7, R7 }
188 punpckldq m2, m5 ; (byte) { B4, G4, R4, B5, B6, G6, R6, B7 }
189 punpckldq m3, m6 ; (byte) { R4, B5, G5, R5, R6, B7, G7, R7 }
192 punpcklbw m2, m7 ; (word) { B4, G4, R4, B5, B6, G6, R6, B7 }
193 punpcklbw m3, m7 ; (word) { R4, B5, G5, R5, R6, B7, G7, R7 }
199 pmaddwd m3, coeff2 ; (dword) { R4*RY, G5+GY + R5*RY, R6*RY, G7+GY + R7*RY }
285 pshufb m5, m4, shuf_rgb2 ; (word) { R4, B5, G5, R5, R6, B
[all...]
H A Dyuv_2_rgb.asm200 paddsw m1, m6 ; R0 R2 R4 R6 ...
205 packuswb m0, m3 ; R0 R2 R4 R6 ... R1 R3 R5 R7 ...
211 punpcklbw m3, m2 ; R0 G0 R2 G2 R4 G4 R6 G6 R8 G8 ...
217 punpckhwd m5, m6 ; R4 G4 B4 R5 R6 G6 B6 R7
224 pand m7, [mask_0110] ; -- -- R6 G6 B6 R7 -- --
250 movd [imageq + 18], m5 ; R6 G6 B6 R7
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/include/llvm/Support/
H A DMathExtras.h224 #define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4) macro
225 R6(0), R6(2), R6(1), R6(3)
228 #undef R6 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h48 case R4: case R5: case R6: case R7: in isARMArea1Register()
102 unsigned BasePtr = ARM::R6;
H A DThumb1FrameLowering.cpp221 case ARM::R6: in emitPrologue()
286 case ARM::R6: in emitPrologue()
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) { in spillCalleeSavedRegisters()
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6, in spillCalleeSavedRegisters()
985 ARM::R4, ARM::R5, ARM::R6, ARM::R7}; in restoreCalleeSavedRegisters()
H A DARMFrameLowering.cpp435 case ARM::R6: in emitPrologue()
642 case ARM::R6: in emitPrologue()
1735 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. in determineCalleeSaves()
1743 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1759 case ARM::R6: case ARM::R7: in determineCalleeSaves()
1945 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) { in determineCalleeSaves()
2028 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. in determineCalleeSaves()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
H A DMathExtras.h296 #define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4) macro
297 R6(0), R6(2), R6(1), R6(3)
300 #undef R6 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBPFFrameLowering.cpp35 SavedRegs.reset(BPF::R6); in determineCalleeSaves()
H A DBPFISelDAGToDAG.cpp217 SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64); in Select()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
210 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiBaseInfo.h57 case Lanai::R6: in getLanaiRegisterNumbering()
/third_party/ffmpeg/libavcodec/x86/
H A Dvp3dsp.asm277 psubsw m6, m5 ; r6 = R6 = F. - B..
306 psubsw m6, m5 ; r6 = R6 = F. - B..
308 paddsw m6, OC_8 ; adjust R6 (and R5) for shift
373 punpckldq m1, m0 ; r1 = h2 g2 f2 e2 = R6
484 psubsw m6, m5 ; xmm6 = F. - B..= R6
486 ADD(m6) ; Adjust R6 and R5 before shifting
H A Dsimple_idct.asm85 movq mm1, [blockq + %2] ; R6 R2 r6 r2
174 movq mm1, [blockq + %2] ; R6 R2 r6 r2
251 movq mm1, %2 ; R6 R2 r6 r2
326 movq mm1, %2 ; R6 R2 r6 r2
563 movq mm1, [%2] ; R6 R2 r6 r2
579 movq mm3, [8 + %2] ; R6 R2 r6 r2
617 movq mm1, %2 ; R6 R2 r6 r2
/third_party/ltp/testcases/kernel/syscalls/ptrace/
H A Dptrace04.c34 R(R0) R(R1) R(R2) R(R3) R(R4) R(R5) R(R6) R(R7)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 in getCallerSavedRegs()
349 return Hexagon::R6; in getFirstCallerSavedNonParamReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp214 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
219 XCore::R4, XCore::R5, XCore::R6, XCore::R7, in getCalleeSavedRegs()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h164 case R4: case R5: case R6: case R7: in isARMLowRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp157 Lanai::R6, Lanai::R7, Lanai::RV, Lanai::R9, Lanai::RR1, Lanai::RR2,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp114 ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp86 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,

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