| /third_party/ltp/tools/sparse/sparse-src/validation/ |
| H A D | repeat.h | 13 #define R12(P, S) R9(P,S##0) R9(P,S##1) R9(P,S##2) R9(P,S##3) R9(P,S##4) R9(P,S##5) R9(P,S##6) R9(P,S##7) macro
14 #define R13(P, S) R12(P,S##0) R12(P,S##1)
15 #define R14(P, S) R12(P,S##0) R12(P,S##1) R12(P,S##2) R12(P,S##3)
16 #define R15(P, S) R12(P,S##0) R12(P,S##1) R12(
[all...] |
| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | simple_idct_arm.S | 50 @@ R12 is another scratch register, so it should not be saved too
54 add r14, r0, #112 @ R14=&block[8*7], better start from the last row, and decrease the value until row=0, i.e. R12=block.
63 @@ at this point, R0=block, R14=&block[56], R12=__const_ptr_, R1-R11 free
68 ldr r1, [r14, #0] @ R1=(int32)(R12)[0]=ROWr32[0] (relative row cast to a 32b pointer)
69 ldr r2, [r14, #4] @ R2=(int32)(R12)[1]=ROWr32[1]
75 @@ at this point, R0=block, R14=&block[n], R12=__const_ptr_, R1=ROWr32[0], R2=ROWr32[1],
89 @@ R12=__const_ptr_, R14=&block[n]
120 @@ R12=__const_ptr_, R14=&block[n]
128 @@ R12=__const_ptr_, R14=&block[n]
160 @@ R12
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/marl/src/ |
| H A D | osfiber_asm_x64.h | 40 uintptr_t R12; member
60 static_assert(offsetof(marl_fiber_context, R12) == MARL_REG_R12,
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| /third_party/libunwind/libunwind/src/x86_64/ |
| H A D | init.h | 61 c->dwarf.loc[R12] = REG_INIT_LOC(c, r12, R12); in common_init()
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| H A D | unwind_i.h | 51 #define R12 12 macro
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| H A D | Gget_save_loc.c | 43 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break; in unw_get_save_loc()
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| H A D | Gregs.c | 117 case UNW_X86_64_R12: loc = c->dwarf.loc[R12]; break; in tdep_access_reg()
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| H A D | Gos-solaris.c | 84 c->dwarf.loc[R12] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R12, 0); in x86_64_handle_signal_frame()
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| H A D | Gos-freebsd.c | 123 c->dwarf.loc[R12] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R12, 0); in x86_64_handle_signal_frame()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 51 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
63 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
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| H A D | ARMFrameLowering.cpp | 423 case ARM::R12: in emitPrologue()
544 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
550 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
632 case ARM::R12: in emitPrologue()
665 case ARM::R12: in emitPrologue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.cpp | 54 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
60 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, in getCalleeSavedRegs()
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| H A D | MSP430ISelLowering.cpp | 460 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
465 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 in AnalyzeArguments()
783 unsigned R12 = MSP430::R12; in LowerReturn() local
785 Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag); in LowerReturn()
787 RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout()))); in LowerReturn()
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| /third_party/musl/arch/x32/bits/ |
| H A D | reg.h | 6 #define R12 3 macro
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| /third_party/musl/arch/x86_64/bits/ |
| H A D | reg.h | 6 #define R12 3 macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 159 StackSlotsUsedByFunclet = Last - ARC::R12; in emitPrologue()
271 StackSlotsUsedByFunclet = Last - ARC::R12; in emitEpilogue()
373 for (unsigned Which = Last; Which > ARC::R12; Which--) { in assignCalleeSavedSpillSlots()
386 if (I.getReg() > ARC::R12) in assignCalleeSavedSpillSlots()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 168 {codeview::RegisterId::R12, X86::R12}, in initLLVMToSEHAndCVRegMapping()
651 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
688 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
724 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
760 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: in getX86SubSuperRegisterOrZero()
761 return X86::R12; in getX86SubSuperRegisterOrZero()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiBaseInfo.h | 72 case Lanai::R12: in getLanaiRegisterNumbering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 354 Value *R11, *R12; in getMaskedTypeForICmpPair() local
356 if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) { in getMaskedTypeForICmpPair()
359 D = R12; in getMaskedTypeForICmpPair()
360 } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) { in getMaskedTypeForICmpPair()
361 A = R12; in getMaskedTypeForICmpPair()
370 if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) { in getMaskedTypeForICmpPair()
374 R12 in getMaskedTypeForICmpPair()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 597 - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
601 - If the defaults (R0/R12) are available, return true
620 unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; in findScratchRegister() local
628 *SR2 = R12; in findScratchRegister()
631 // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. in findScratchRegister()
652 // Note that we only return here if both R0 and R12 are available because in findScratchRegister()
655 if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) in findScratchRegister()
837 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg in emitPrologue()
838 // ...(R12/X1 in emitPrologue()
[all...] |
| /third_party/rust/crates/libc/src/fuchsia/ |
| H A D | x86_64.rs | 124 pub const R12: ::c_int = 3; consts
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 185 ENTRY(R12) \
203 ENTRY(R12) \
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 158 Lanai::R12, Lanai::R13, Lanai::R14, Lanai::RCA, Lanai::R16, Lanai::R17,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 115 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 in getCallerSavedRegs()
|