| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.cpp | 43 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
48 MSP430::R8, MSP430::R9, MSP430::R10, in getCalleeSavedRegs()
53 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
59 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, in getCalleeSavedRegs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 38 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_AlignArgRegs()
63 PPC::R7, PPC::R8, PPC::R9, PPC::R10, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
115 static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 }; in CC_PPC32_SPE_CustomSplitFP64()
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| /third_party/ffmpeg/libavcodec/arm/ |
| H A D | simple_idct_arm.S | 104 ldr r10, =W5 @ R10=W5
119 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
127 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
159 @@ R5=b2, R6=ROWr16[0], R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
170 ldr r10, =W6 @ R10=W6
189 @@ R5=b2, R6=a0, R7=b3, R8=W2, R9=W4, R10=W6, R11 (free),
213 mulne r10, r8, r9 @ R10=W2*ROWr16[6]
225 @@ R5=b2, R6=a0, R7=b3, R8 (free), R9 (free), R10 (free), R11 (free),
239 ldr r10, =MASK_MSHW @ R10=0xFFFF0000
241 mvn r11, r10 @ R11= NOT R10
[all...] |
| /third_party/libunwind/libunwind/src/x86_64/ |
| H A D | init.h | 59 c->dwarf.loc[R10] = REG_INIT_LOC(c, r10, R10); in common_init()
|
| H A D | unwind_i.h | 49 #define R10 10 macro
|
| H A D | Gos-freebsd.c | 121 c->dwarf.loc[R10] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R10, 0); in x86_64_handle_signal_frame()
133 c->dwarf.loc[RCX] = c->dwarf.loc[R10]; in x86_64_handle_signal_frame()
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| H A D | Gregs.c | 115 case UNW_X86_64_R10: loc = c->dwarf.loc[R10]; break; in tdep_access_reg()
|
| H A D | Gos-solaris.c | 82 c->dwarf.loc[R10] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_R10, 0); in x86_64_handle_signal_frame()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 51 case R8: case R9: case R10: case R11: case R12: in isARMArea1Register()
63 case R8: case R9: case R10: case R11: case R12: in isARMArea2Register()
|
| H A D | Thumb1FrameLowering.cpp | 212 case ARM::R10: in emitPrologue()
274 case ARM::R10: in emitPrologue()
355 case ARM::R10: in emitPrologue()
877 static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8}; in spillCalleeSavedRegisters()
986 static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11}; in restoreCalleeSavedRegisters()
|
| /third_party/musl/arch/x32/bits/ |
| H A D | reg.h | 10 #define R10 7 macro
|
| /third_party/musl/arch/x86_64/bits/ |
| H A D | reg.h | 10 #define R10 7 macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 166 {codeview::RegisterId::R10, X86::R10}, in initLLVMToSEHAndCVRegMapping()
647 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
684 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
720 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
756 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: in getX86SubSuperRegisterOrZero()
757 return X86::R10; in getX86SubSuperRegisterOrZero()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiBaseInfo.h | 66 case Lanai::R10: in getLanaiRegisterNumbering()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 215 XCore::R8, XCore::R9, XCore::R10, in getCalleeSavedRegs()
238 Reserved.set(XCore::R10); in getReservedRegs()
327 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; in getFrameRegister()
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| H A D | XCoreFrameLowering.cpp | 34 static const unsigned FramePtr = XCore::R10;
435 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && in spillCalleeSavedRegisters()
465 assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) && in restoreCalleeSavedRegisters()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| H A D | BPFRegisterInfo.cpp | 125 return BPF::R10;
|
| /third_party/rust/crates/libc/src/fuchsia/ |
| H A D | x86_64.rs | 128 pub const R10: ::c_int = 7; consts
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 183 ENTRY(R10) \
201 ENTRY(R10) \
|
| /third_party/ltp/tools/sparse/sparse-src/validation/ |
| H A D | repeat.h | 11 #define R10(P, S) R9(P,S##0) R9(P,S##1) macro
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/ |
| H A D | BPFDisassembler.cpp | 98 BPF::R6, BPF::R7, BPF::R8, BPF::R9, BPF::R10, BPF::R11};
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiRegisterInfo.cpp | 54 Reserved.set(Lanai::R10); in getReservedRegs()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 115 ARC::R7, ARC::R8, ARC::R9, ARC::R10, ARC::R11, ARC::R12, ARC::R13,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 60 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0 in getCallerSavedRegs()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 87 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
|