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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp76 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
87 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg()
89 return S[R-Hexagon::Q0]; in getStringReg()
191 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()
192 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n'); in runOnMachineFunction()
H A DHexagonRegisterInfo.cpp77 Q0, Q1, Q2, Q3, 0 in getCallerSavedRegs()
/third_party/ffmpeg/libavcodec/
H A Dcavsdsp.c41 #define Q0 p0_p[ 0*stride] macro
48 int q0 = Q0; in loop_filter_l2()
59 Q0 = (Q1 + q0 + s) >> 2; in loop_filter_l2()
62 Q0 = (2*Q1 + s) >> 2; in loop_filter_l2()
69 int q0 = Q0; in loop_filter_l1()
74 Q0 = av_clip_uint8(q0-delta); in loop_filter_l1()
76 delta = av_clip(((P0-P1)*3+P2-Q0+4)>>3, -tc, tc); in loop_filter_l1()
80 delta = av_clip(((Q1-Q0)*3+P0-Q2+4)>>3, -tc, tc); in loop_filter_l1()
89 int q0 = Q0; in loop_filter_c2()
99 Q0 in loop_filter_c2()
118 #undef Q0 global() macro
[all...]
H A Dhevcdsp_template.c1501 #define Q0 pix[0 * xstride] macro
1530 const int dq0 = abs(Q2 - 2 * Q1 + Q0); in hevc_loop_filter_luma()
1547 if (abs(P3 - P0) + abs(Q3 - Q0) < beta_3 && abs(P0 - Q0) < tc25 && in hevc_loop_filter_luma()
1557 const int q0 = Q0; in hevc_loop_filter_luma()
1567 Q0 = q0 + av_clip(((p1 + 2 * p0 + 2 * q0 + 2 * q1 + q2 + 4) >> 3) - q0, -tc2, tc2); in hevc_loop_filter_luma()
1586 const int q0 = Q0; in hevc_loop_filter_luma()
1595 Q0 = av_clip_pixel(q0 - delta0); in hevc_loop_filter_luma()
1634 const int q0 = Q0; in hevc_loop_filter_chroma()
1640 Q0 in hevc_loop_filter_chroma()
1680 #undef Q0 global() macro
[all...]
/third_party/ffmpeg/libavcodec/x86/
H A Dvp9lpf.asm326 %define Q0 dstq + 4* strideq + %1
341 %define Q0 rsp + 4*mmsize + %1
425 movx m8, [Q0]
463 mova [Q0], m8
492 movx m0, [Q0]
521 movx m1, [Q0]
535 TRANSPOSE8x8W 0, 2, 4, 6, 1, 5, 7, 3, [rsp], [Q0], 1
558 mova [Q0], m1
591 mova m12, [Q0]
616 %define rq0 [Q0]
[all...]
H A Dvp9lpf_16bpp.asm541 PRELOAD 10, %%q0, Q0
/third_party/musl/porting/liteos_a/kernel/src/math/
H A Dexpm1l.c68 Q0 = -9.516813471998079611319047060563358064497E4L, variable
106 qx = (((( x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1l()
/third_party/musl/src/math/
H A Dexpm1l.c68 Q0 = -9.516813471998079611319047060563358064497E4L, variable
106 qx = (((( x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1l()
/third_party/ffmpeg/libavcodec/arm/
H A Dvp8dsp_neon.S275 vabd.u8 q9, q3, q4 @ abs(P0-Q0)
277 vqadd.u8 q9, q9, q9 @ abs(P0-Q0) * 2
279 vqadd.u8 q11, q9, q10 @ (abs(P0-Q0)*2) + (abs(P1-Q1)/2)
281 vcle.u8 q8, q11, q14 @ (abs(P0-Q0)*2) + (abs(P1-Q1)/2) <= flim
285 vabd.u8 q13, q5, q4 @ abs(Q1-Q0)
289 vcle.u8 q9, q13, q15 @ abs(Q1-Q0) <= flim_I
299 vabd.u8 q9, q3, q4 @ abs(P0-Q0)
302 vqadd.u8 q9, q9, q9 @ abs(P0-Q0) * 2
306 vqadd.u8 q11, q9, q10 @ (abs(P0-Q0)*2) + (abs(P1-Q1)/2)
308 vcle.u8 q11, q11, q14 @ (abs(P0-Q0)*
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
H A DAArch64AsmPrinter.cpp944 DestReg = AArch64::Q0 + (DestReg - AArch64::H0); in EmitFMov0()
946 DestReg = AArch64::Q0 + (DestReg - AArch64::S0); in EmitFMov0()
949 DestReg = AArch64::Q0 + (DestReg - AArch64::D0); in EmitFMov0()
H A DAArch64PBQPRegAlloc.cpp128 case AArch64::Q0: in isOdd()
/third_party/mesa3d/src/mesa/main/
H A Dtexcompress_astc.cpp169 uint8_t Q0 = (in >> (n)) & 0x1; in unpack_quint_block() local
184 q2 = CAT_BITS_3(Q0, Q4 & ~Q0, Q3 & ~Q0); in unpack_quint_block()
190 C = CAT_BITS_5(Q4, Q3, 0x1 & ~Q6, 0x1 & ~Q5, Q0); in unpack_quint_block()
193 C = CAT_BITS_5(Q4, Q3, Q2, Q1, Q0); in unpack_quint_block()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp164 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1165 case AArch64::Q0: Reg = AArch64::Q1; break; in getNextVectorRegister()
1198 Reg = AArch64::Q0; in getNextVectorRegister()
1572 case 128: Base = AArch64::Q0; break; in printZPRasFPR()
H A DAArch64MCTargetDesc.cpp195 {codeview::RegisterId::ARM64_Q0, AArch64::Q0}, in initLLVMToCVRegMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/
H A Dassembler_arm.cc1276 EmitSIMDqqq(B25 | B24 | B23 | B10 | B8 | B7, kWordPair, qd, Q0, qm);
1292 qd, Q0, qm);
1298 qd, Q0, qm);
1304 Q0, qm);
1313 qd, Q0, qm);
1359 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp91 SP::Q0, SP::Q8, ~0U, ~0U,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1462 case 128: Base = AArch64::Q0; break; in addFPRasZPRRegOperands()
1473 Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0)); in addVectorReg64Operands()
1498 /* DReg */ { AArch64::Q0, in addVectorListOperands()
1501 /* QReg */ { AArch64::Q0, in addVectorListOperands()
1502 AArch64::Q0, AArch64::Q0_Q1, in addVectorListOperands()
2090 .Case("v0", AArch64::Q0) in MatchNeonVectorRegName()
3887 (ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) || in isMatchingOrAlias()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp305 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
629 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp638 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, in DecodeHvxQRRegisterClass()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp579 case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: in getMachineOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp159 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp129 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7). in CC_Sparc64_Full()
130 Reg = SP::Q0 + Offset/16; in CC_Sparc64_Full()
1063 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; in fixupVariableFloatArgs()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringARM32.cpp5743 Variable *Q0 = legalizeToReg(Src0, RegARM32::Reg_q0);
5744 Reg = Q0;

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