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Searched refs:PreIndex (Results 1 - 25 of 45) sorted by relevance

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/third_party/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc1600 {{al, r0, r2, minus, 3194, PreIndex},
1603 "al r0 r2 minus 3194 PreIndex",
1610 {{al, r5, r6, plus, 1437, PreIndex},
1613 "al r5 r6 plus 1437 PreIndex",
1625 {{al, r5, r0, plus, 1066, PreIndex},
1628 "al r5 r0 plus 1066 PreIndex",
1630 {{al, r11, r6, minus, 3069, PreIndex},
1633 "al r11 r6 minus 3069 PreIndex",
1635 {{al, r12, r3, plus, 595, PreIndex},
1638 "al r12 r3 plus 595 PreIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-rs-a32.cc1604 {{al, r2, r5, plus, r9, PreIndex},
1607 "al r2 r5 plus r9 PreIndex",
1609 {{al, r8, r14, plus, r9, PreIndex},
1612 "al r8 r14 plus r9 PreIndex",
1614 {{al, r2, r10, minus, r3, PreIndex},
1617 "al r2 r10 minus r3 PreIndex",
1624 {{al, r1, r2, plus, r4, PreIndex},
1627 "al r1 r2 plus r4 PreIndex",
1634 {{al, r1, r8, plus, r6, PreIndex},
1637 "al r1 r8 plus r6 PreIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-immediate-512-a32.cc1610 {{al, r5, r3, minus, 99, PreIndex},
1613 "al r5 r3 minus 99 PreIndex",
1620 {{al, r13, r12, plus, 161, PreIndex},
1623 "al r13 r12 plus 161 PreIndex",
1625 {{al, r4, r13, minus, 132, PreIndex},
1628 "al r4 r13 minus 132 PreIndex",
1635 {{al, r11, r14, minus, 116, PreIndex},
1638 "al r11 r14 minus 116 PreIndex",
1645 {{al, r8, r4, minus, 198, PreIndex},
1648 "al r8 r4 minus 198 PreIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-immediate-512-a32.cc2328 {{al, r14, r9, plus, 41, PreIndex},
2329 "al r14 r9 plus 41 PreIndex",
2333 {{al, r7, r9, plus, 78, PreIndex},
2334 "al r7 r9 plus 78 PreIndex",
2338 {{al, r6, r3, plus, 255, PreIndex},
2339 "al r6 r3 plus 255 PreIndex",
2343 {{al, r11, r8, plus, 139, PreIndex},
2344 "al r11 r8 plus 139 PreIndex",
2348 {{al, r6, r3, plus, 170, PreIndex},
2349 "al r6 r3 plus 170 PreIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-immediate-8192-a32.cc2328 {{al, r14, r12, plus, 2982, PreIndex},
2329 "al r14 r12 plus 2982 PreIndex",
2333 {{al, r7, r11, plus, 1241, PreIndex},
2334 "al r7 r11 plus 1241 PreIndex",
2338 {{al, r6, r5, plus, 2677, PreIndex},
2339 "al r6 r5 plus 2677 PreIndex",
2343 {{al, r11, r12, plus, 2403, PreIndex},
2344 "al r11 r12 plus 2403 PreIndex",
2348 {{al, r6, r5, plus, 1274, PreIndex},
2349 "al r6 r5 plus 1274 PreIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-rs-a32.cc2335 {{al, r12, r9, plus, r0, PreIndex},
2336 "al r12 r9 plus r0 PreIndex",
2340 {{al, r0, r4, plus, r11, PreIndex},
2341 "al r0 r4 plus r11 PreIndex",
2345 {{al, r14, r8, plus, r7, PreIndex},
2346 "al r14 r8 plus r7 PreIndex",
2350 {{al, r2, r1, plus, r8, PreIndex},
2351 "al r2 r1 plus r8 PreIndex",
2355 {{al, r7, r9, plus, r5, PreIndex},
2356 "al r7 r9 plus r5 PreIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc1602 {{al, r8, r0, plus, r1, ASR, 3, PreIndex},
1605 "al r8 r0 plus r1 ASR 3 PreIndex",
1607 {{al, r0, r14, minus, r6, ASR, 27, PreIndex},
1610 "al r0 r14 minus r6 ASR 27 PreIndex",
1622 {{al, r2, r5, plus, r6, ASR, 7, PreIndex},
1625 "al r2 r5 plus r6 ASR 7 PreIndex",
1632 {{al, r0, r11, minus, r1, ASR, 13, PreIndex},
1635 "al r0 r11 minus r1 ASR 13 PreIndex",
1637 {{al, r13, r12, plus, r6, LSR, 16, PreIndex},
1640 "al r13 r12 plus r6 LSR 16 PreIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc1602 {{al, r8, r3, minus, r4, ROR, 30, PreIndex},
1605 "al r8 r3 minus r4 ROR 30 PreIndex",
1607 {{al, r1, r0, plus, r5, LSL, 13, PreIndex},
1610 "al r1 r0 plus r5 LSL 13 PreIndex",
1622 {{al, r2, r6, plus, r7, ROR, 18, PreIndex},
1625 "al r2 r6 plus r7 ROR 18 PreIndex",
1627 {{al, r0, r11, minus, r11, ROR, 26, PreIndex},
1630 "al r0 r11 minus r11 ROR 26 PreIndex",
1632 {{al, r14, r4, plus, r14, LSL, 12, PreIndex},
1635 "al r14 r4 plus r14 LSL 12 PreIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc2333 {{al, r4, r9, plus, r3, LSL, 2, PreIndex},
2334 "al r4 r9 plus r3 LSL 2 PreIndex",
2338 {{al, r1, r9, plus, r10, LSL, 25, PreIndex},
2339 "al r1 r9 plus r10 LSL 25 PreIndex",
2343 {{al, r14, r1, plus, r12, ROR, 24, PreIndex},
2344 "al r14 r1 plus r12 ROR 24 PreIndex",
2348 {{al, r3, r10, plus, r14, LSL, 24, PreIndex},
2349 "al r3 r10 plus r14 LSL 24 PreIndex",
2353 {{al, r10, r5, plus, r0, LSL, 17, PreIndex},
2354 "al r10 r5 plus r0 LSL 17 PreIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc2333 {{al, r4, r7, plus, r5, LSR, 28, PreIndex},
2334 "al r4 r7 plus r5 LSR 28 PreIndex",
2338 {{al, r1, r9, plus, r0, LSR, 17, PreIndex},
2339 "al r1 r9 plus r0 LSR 17 PreIndex",
2343 {{al, r12, r9, plus, r7, ASR, 17, PreIndex},
2344 "al r12 r9 plus r7 ASR 17 PreIndex",
2348 {{al, r3, r9, plus, r6, LSR, 2, PreIndex},
2349 "al r3 r9 plus r6 LSR 2 PreIndex",
2353 {{al, r10, r0, plus, r11, ASR, 9, PreIndex},
2354 "al r10 r0 plus r11 ASR 9 PreIndex",
[all...]
H A Dtest-disasm-a32.cc655 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PreIndex)), in TEST()
659 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PreIndex)), in TEST()
662 COMPARE_A32(Ldr(r0, MemOperand(r1, -0xff123, PreIndex)), in TEST()
666 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PreIndex)), in TEST()
670 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PreIndex)), in TEST()
673 COMPARE_T32(Ldr(r0, MemOperand(r1, -0xff12, PreIndex)), in TEST()
723 MUST_FAIL_TEST_BOTH(Ldr(r0, MemOperand(r0, 0xfff12, PreIndex)), in TEST()
756 COMPARE_T32(Ldr(r0, MemOperand(r1, minus, r2, PreIndex)), in TEST()
771 COMPARE_A32(Ldr(pc, MemOperand(r0, r0, PreIndex)), "ldr pc, [r0, r0]!\n"); in TEST()
772 COMPARE_T32(Ldr(pc, MemOperand(r0, r0, PreIndex)), in TEST()
[all...]
/third_party/vixl/test/aarch64/
H A Dtest-disasm-aarch64.cc982 COMPARE(st2g(x30, MemOperand(x4, 160, PreIndex)), "st2g x30, [x4, #160]!"); in TEST()
987 COMPARE(stg(sp, MemOperand(x1, -16, PreIndex)), "stg sp, [x1, #-16]!"); in TEST()
991 COMPARE(stgp(x17, x7, MemOperand(x18, -64, PreIndex)), in TEST()
997 COMPARE(stzg(sp, MemOperand(x1, 32, PreIndex)), "stzg sp, [x1, #32]!"); in TEST()
1001 COMPARE(stz2g(sp, MemOperand(sp, -384, PreIndex)), "stz2g sp, [sp, #-384]!"); in TEST()
1008 COMPARE_MACRO(St2g(x30, MemOperand(x4, 3216, PreIndex)), in TEST()
1014 COMPARE_MACRO(Stg(sp, MemOperand(sp, 4080, PreIndex)), in TEST()
1020 COMPARE_MACRO(Stgp(x27, x7, MemOperand(sp, -672, PreIndex)), in TEST()
1026 COMPARE_MACRO(Stz2g(x3, MemOperand(x4, 272, PreIndex)), in TEST()
1032 COMPARE_MACRO(Stzg(x2, MemOperand(x15, 784, PreIndex)), in TEST()
[all...]
H A Dtest-disasm-neon-aarch64.cc89 COMPARE(ldr(s0, MemOperand(x1, 4, PreIndex)), "ldr s0, [x1, #4]!"); in TEST()
90 COMPARE(ldr(s2, MemOperand(x3, 255, PreIndex)), "ldr s2, [x3, #255]!"); in TEST()
91 COMPARE(ldr(s4, MemOperand(x5, -256, PreIndex)), "ldr s4, [x5, #-256]!"); in TEST()
92 COMPARE(ldr(d6, MemOperand(x7, 8, PreIndex)), "ldr d6, [x7, #8]!"); in TEST()
93 COMPARE(ldr(d8, MemOperand(x9, 255, PreIndex)), "ldr d8, [x9, #255]!"); in TEST()
94 COMPARE(ldr(d10, MemOperand(x11, -256, PreIndex)), "ldr d10, [x11, #-256]!"); in TEST()
96 COMPARE(str(s12, MemOperand(x13, 4, PreIndex)), "str s12, [x13, #4]!"); in TEST()
97 COMPARE(str(s14, MemOperand(x15, 255, PreIndex)), "str s14, [x15, #255]!"); in TEST()
98 COMPARE(str(s16, MemOperand(x17, -256, PreIndex)), "str s16, [x17, #-256]!"); in TEST()
99 COMPARE(str(d18, MemOperand(x19, 8, PreIndex)), "st in TEST()
[all...]
H A Dtest-assembler-aarch64.cc2969 case PreIndex:
3022 case PreIndex:
3086 MTEStoreTagHelper(&MacroAssembler::St2g, PreIndex, StgPairTag);
3092 MTEStoreTagHelper(&MacroAssembler::Stg, PreIndex);
3098 MTEStoreTagHelper(&MacroAssembler::Stz2g, PreIndex, StgPairTag | StgZeroing);
3104 MTEStoreTagHelper(&MacroAssembler::Stzg, PreIndex, StgZeroing);
3184 __ Stgp(x4, x5, MemOperand(base, offset, PreIndex));
3191 __ Stgp(x5, x6, MemOperand(base, offset, PreIndex));
3198 __ Stgp(x6, x7, MemOperand(base, offset, PreIndex));
3323 __ Ldr(w2, MemOperand(x26, 6144 * sizeof(src[0]), PreIndex));
[all...]
H A Dtest-cpu-features-aarch64.cc288 TEST_NONE(ldpsw_2, ldpsw(x0, x1, MemOperand(x2, 104, PreIndex)))
291 TEST_NONE(ldp_2, ldp(w0, w1, MemOperand(x2, -252, PreIndex)))
294 TEST_NONE(ldp_5, ldp(x0, x1, MemOperand(x2, 360, PreIndex)))
296 TEST_NONE(ldrb_1, ldrb(w0, MemOperand(x1, -137, PreIndex)))
302 TEST_NONE(ldrh_1, ldrh(w0, MemOperand(x1, 52, PreIndex)))
307 TEST_NONE(ldrsb_1, ldrsb(w0, MemOperand(x1, -253, PreIndex)))
310 TEST_NONE(ldrsb_4, ldrsb(x0, MemOperand(x1, 11, PreIndex)))
319 TEST_NONE(ldrsh_1, ldrsh(w0, MemOperand(x1, -34, PreIndex)))
322 TEST_NONE(ldrsh_4, ldrsh(x0, MemOperand(x1, 72, PreIndex)))
329 TEST_NONE(ldrsw_1, ldrsw(x0, MemOperand(x1, 13, PreIndex)))
[all...]
H A Dtest-trace-aarch64.cc171 __ ldp(w23, w24, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase()
174 __ ldp(x25, x26, MemOperand(x1, 16, PreIndex)); in GenerateTestSequenceBase()
177 __ ldpsw(x27, x28, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase()
180 __ ldr(w29, MemOperand(x1, 4, PreIndex)); in GenerateTestSequenceBase()
183 __ ldr(x2, MemOperand(x1, 8, PreIndex)); in GenerateTestSequenceBase()
186 __ ldrb(w3, MemOperand(x1, 1, PreIndex)); in GenerateTestSequenceBase()
189 __ ldrb(x4, MemOperand(x1, 1, PreIndex)); in GenerateTestSequenceBase()
192 __ ldrh(w5, MemOperand(x1, 2, PreIndex)); in GenerateTestSequenceBase()
195 __ ldrh(x6, MemOperand(x1, 2, PreIndex)); in GenerateTestSequenceBase()
198 __ ldrsb(w7, MemOperand(x1, 1, PreIndex)); in GenerateTestSequenceBase()
[all...]
/third_party/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.cc1746 case PreIndex: in Delegate()
1762 MemOperand(rn, load_store_offset, PreIndex)); in Delegate()
1839 case PreIndex: in Delegate()
1968 case PreIndex: { in Delegate()
1989 MemOperand(rn, load_store_offset, PreIndex)); in Delegate()
2048 case PreIndex: in Delegate()
2133 case PreIndex: in Delegate()
2206 case PreIndex: in Delegate()
H A Doperands-aarch32.h829 bool IsPreIndex() const { return GetAddrMode() == PreIndex; } in IsPreIndex()
879 VIXL_ASSERT(addrmode != PreIndex); in AlignedMemOperand()
887 VIXL_ASSERT(addrmode != PreIndex); in AlignedMemOperand()
H A Doperands-aarch32.cc544 } else if (operand.GetAddrMode() == PreIndex) { in operator <<()
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc2243 Stp(bottom_0, bottom_1, MemOperand(StackPointer(), -size, PreIndex)); in Emit()
2245 Str(bottom_0, MemOperand(StackPointer(), -size, PreIndex)); in Emit()
2340 str(src0, MemOperand(StackPointer(), -1 * size, PreIndex)); in Emit()
2344 stp(src1, src0, MemOperand(StackPointer(), -2 * size, PreIndex)); in Emit()
2348 stp(src2, src1, MemOperand(StackPointer(), -3 * size, PreIndex)); in Emit()
2355 stp(src3, src2, MemOperand(StackPointer(), -4 * size, PreIndex)); in Emit()
2503 MemOperand tos(sp, -2 * static_cast<int>(kXRegSizeInBytes), PreIndex); in Emit()
H A Doperands-aarch64.cc355 bool MemOperand::IsPreIndex() const { return addrmode_ == PreIndex; } in IsPreIndex()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dinstructions-arm64.h64 enum AddrMode { Offset, PreIndex, PostIndex }; enumerator
H A Dmacro-assembler-arm64.cc1191 str(src0, MemOperand(sp, -1 * size, PreIndex)); in PushHelper()
1195 stp(src1, src0, MemOperand(sp, -2 * size, PreIndex)); in PushHelper()
1199 stp(src2, src1, MemOperand(sp, -3 * size, PreIndex)); in PushHelper()
1206 stp(src3, src2, MemOperand(sp, -4 * size, PreIndex)); in PushHelper()
1271 MemOperand tos(sp, -2 * static_cast<int>(kXRegSize), PreIndex); in PushCalleeSavedRegisters()
/third_party/node/deps/v8/src/codegen/arm/
H A Dconstants-arm.h260 PreIndex = (8 | 4 | 1) << 21, // Pre-indexed addressing with writeback. enumerator
/third_party/vixl/benchmarks/aarch64/
H A Dbench-utils.cc262 __ Ldrsw(PickX(), MemOperand(scratch, -42, PreIndex)); in GenerateMemOperandSequence()

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