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Searched refs:PostIndex (Results 1 - 25 of 57) sorted by relevance

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/third_party/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-memop-immediate-512-a32.cc1600 {{al, r0, r2, minus, 180, PostIndex},
1603 "al r0 r2 minus 180 PostIndex",
1605 {{al, r7, r10, plus, 36, PostIndex},
1608 "al r7 r10 plus 36 PostIndex",
1615 {{al, r0, r8, plus, 182, PostIndex},
1618 "al r0 r8 plus 182 PostIndex",
1630 {{al, r11, r3, minus, 116, PostIndex},
1633 "al r11 r3 minus 116 PostIndex",
1640 {{al, r7, r1, plus, 13, PostIndex},
1643 "al r7 r1 plus 13 PostIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-rs-a32.cc1619 {{al, r9, r4, plus, r7, PostIndex},
1622 "al r9 r4 plus r7 PostIndex",
1629 {{al, r5, r9, minus, r14, PostIndex},
1632 "al r5 r9 minus r14 PostIndex",
1644 {{al, r14, r7, minus, r5, PostIndex},
1647 "al r14 r7 minus r5 PostIndex",
1649 {{al, r1, r11, plus, r14, PostIndex},
1652 "al r1 r11 plus r14 PostIndex",
1659 {{al, r1, r13, plus, r11, PostIndex},
1662 "al r1 r13 plus r11 PostIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc1605 {{al, r7, r12, plus, 1804, PostIndex},
1608 "al r7 r12 plus 1804 PostIndex",
1615 {{al, r0, r8, minus, 4, PostIndex},
1618 "al r0 r8 minus 4 PostIndex",
1620 {{al, r14, r2, plus, 1635, PostIndex},
1623 "al r14 r2 plus 1635 PostIndex",
1660 {{al, r13, r10, plus, 1459, PostIndex},
1663 "al r13 r10 plus 1459 PostIndex",
1665 {{al, r11, r12, plus, 2490, PostIndex},
1668 "al r11 r12 plus 2490 PostIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc1612 {{al, r13, r3, minus, r1, ROR, 31, PostIndex},
1615 "al r13 r3 minus r1 ROR 31 PostIndex",
1617 {{al, r9, r7, minus, r1, LSL, 8, PostIndex},
1620 "al r9 r7 minus r1 LSL 8 PostIndex",
1647 {{al, r0, r14, plus, r2, LSL, 10, PostIndex},
1650 "al r0 r14 plus r2 LSL 10 PostIndex",
1657 {{al, r0, r4, minus, r12, LSL, 31, PostIndex},
1660 "al r0 r4 minus r12 LSL 31 PostIndex",
1662 {{al, r11, r12, plus, r7, LSL, 25, PostIndex},
1665 "al r11 r12 plus r7 LSL 25 PostIndex",
[all...]
H A Dtest-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc1612 {{al, r12, r11, minus, r8, LSR, 2, PostIndex},
1615 "al r12 r11 minus r8 LSR 2 PostIndex",
1617 {{al, r9, r3, plus, r10, ASR, 28, PostIndex},
1620 "al r9 r3 plus r10 ASR 28 PostIndex",
1627 {{al, r14, r11, minus, r2, ASR, 2, PostIndex},
1630 "al r14 r11 minus r2 ASR 2 PostIndex",
1657 {{al, r0, r13, minus, r4, ASR, 26, PostIndex},
1660 "al r0 r13 minus r4 ASR 26 PostIndex",
1667 {{al, r0, r4, minus, r8, ASR, 21, PostIndex},
1670 "al r0 r4 minus r8 ASR 21 PostIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-immediate-512-a32.cc1328 {{al, r14, r7, plus, 211, PostIndex},
1329 "al r14 r7 plus 211 PostIndex",
1333 {{al, r7, r11, plus, 202, PostIndex},
1334 "al r7 r11 plus 202 PostIndex",
1338 {{al, r11, r3, plus, 175, PostIndex},
1339 "al r11 r3 plus 175 PostIndex",
1343 {{al, r4, r8, plus, 129, PostIndex},
1344 "al r4 r8 plus 129 PostIndex",
1348 {{al, r4, r7, plus, 71, PostIndex},
1349 "al r4 r7 plus 71 PostIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-immediate-8192-a32.cc1328 {{al, r14, r11, plus, 1506, PostIndex},
1329 "al r14 r11 plus 1506 PostIndex",
1333 {{al, r7, r14, plus, 3399, PostIndex},
1334 "al r7 r14 plus 3399 PostIndex",
1338 {{al, r11, r6, plus, 2588, PostIndex},
1339 "al r11 r6 plus 2588 PostIndex",
1343 {{al, r4, r9, plus, 2906, PostIndex},
1344 "al r4 r9 plus 2906 PostIndex",
1348 {{al, r4, r8, plus, 1916, PostIndex},
1349 "al r4 r8 plus 1916 PostIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-rs-a32.cc1335 {{al, r8, r11, plus, r4, PostIndex},
1336 "al r8 r11 plus r4 PostIndex",
1340 {{al, r4, r1, plus, r2, PostIndex},
1341 "al r4 r1 plus r2 PostIndex",
1345 {{al, r0, r7, plus, r5, PostIndex},
1346 "al r0 r7 plus r5 PostIndex",
1350 {{al, r3, r6, plus, r10, PostIndex},
1351 "al r3 r6 plus r10 PostIndex",
1355 {{al, r7, r3, plus, r6, PostIndex},
1356 "al r7 r3 plus r6 PostIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc1333 {{al, r9, r4, plus, r0, ROR, 19, PostIndex},
1334 "al r9 r4 plus r0 ROR 19 PostIndex",
1338 {{al, r2, r3, plus, r8, LSL, 10, PostIndex},
1339 "al r2 r3 plus r8 LSL 10 PostIndex",
1343 {{al, r11, r14, plus, r5, LSL, 31, PostIndex},
1344 "al r11 r14 plus r5 LSL 31 PostIndex",
1348 {{al, r5, r14, plus, r9, ROR, 11, PostIndex},
1349 "al r5 r14 plus r9 ROR 11 PostIndex",
1353 {{al, r6, r1, plus, r5, LSL, 11, PostIndex},
1354 "al r6 r1 plus r5 LSL 11 PostIndex",
[all...]
H A Dtest-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc1333 {{al, r9, r0, plus, r4, LSR, 26, PostIndex},
1334 "al r9 r0 plus r4 LSR 26 PostIndex",
1338 {{al, r2, r1, plus, r9, LSR, 30, PostIndex},
1339 "al r2 r1 plus r9 LSR 30 PostIndex",
1343 {{al, r11, r7, plus, r8, LSR, 13, PostIndex},
1344 "al r11 r7 plus r8 LSR 13 PostIndex",
1348 {{al, r5, r11, plus, r3, ASR, 2, PostIndex},
1349 "al r5 r11 plus r3 ASR 2 PostIndex",
1353 {{al, r5, r12, plus, r11, LSR, 27, PostIndex},
1354 "al r5 r12 plus r11 LSR 27 PostIndex",
[all...]
H A Dtest-disasm-a32.cc677 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PostIndex)), in TEST()
681 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PostIndex)), in TEST()
684 COMPARE_A32(Ldr(r0, MemOperand(r1, -0xff123, PostIndex)), in TEST()
688 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PostIndex)), in TEST()
692 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PostIndex)), in TEST()
695 COMPARE_T32(Ldr(r0, MemOperand(r1, -0xff12, PostIndex)), in TEST()
725 MUST_FAIL_TEST_BOTH(Ldr(r0, MemOperand(r0, 0xfff12, PostIndex)), in TEST()
761 COMPARE_T32(Ldr(r0, MemOperand(r1, minus, r2, PostIndex)), in TEST()
775 COMPARE_A32(Ldr(pc, MemOperand(r0, r0, PostIndex)), "ldr pc, [r0], r0\n"); in TEST()
776 COMPARE_T32(Ldr(pc, MemOperand(r0, r0, PostIndex)), in TEST()
[all...]
/third_party/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc170 __ ldp(w23, w24, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase()
173 __ ldp(x25, x26, MemOperand(x1, 16, PostIndex)); in GenerateTestSequenceBase()
176 __ ldpsw(x27, x28, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase()
179 __ ldr(w29, MemOperand(x1, 4, PostIndex)); in GenerateTestSequenceBase()
182 __ ldr(x2, MemOperand(x1, 8, PostIndex)); in GenerateTestSequenceBase()
185 __ ldrb(w3, MemOperand(x1, 1, PostIndex)); in GenerateTestSequenceBase()
188 __ ldrb(x4, MemOperand(x1, 1, PostIndex)); in GenerateTestSequenceBase()
191 __ ldrh(w5, MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceBase()
194 __ ldrh(x6, MemOperand(x1, 2, PostIndex)); in GenerateTestSequenceBase()
197 __ ldrsb(w7, MemOperand(x1, 1, PostIndex)); in GenerateTestSequenceBase()
[all...]
H A Dtest-disasm-neon-aarch64.cc147 COMPARE(ldr(s0, MemOperand(x1, 4, PostIndex)), "ldr s0, [x1], #4"); in TEST()
148 COMPARE(ldr(s2, MemOperand(x3, 255, PostIndex)), "ldr s2, [x3], #255"); in TEST()
149 COMPARE(ldr(s4, MemOperand(x5, -256, PostIndex)), "ldr s4, [x5], #-256"); in TEST()
150 COMPARE(ldr(d6, MemOperand(x7, 8, PostIndex)), "ldr d6, [x7], #8"); in TEST()
151 COMPARE(ldr(d8, MemOperand(x9, 255, PostIndex)), "ldr d8, [x9], #255"); in TEST()
152 COMPARE(ldr(d10, MemOperand(x11, -256, PostIndex)), "ldr d10, [x11], #-256"); in TEST()
154 COMPARE(str(s12, MemOperand(x13, 4, PostIndex)), "str s12, [x13], #4"); in TEST()
155 COMPARE(str(s14, MemOperand(x15, 255, PostIndex)), "str s14, [x15], #255"); in TEST()
156 COMPARE(str(s16, MemOperand(x17, -256, PostIndex)), "str s16, [x17], #-256"); in TEST()
157 COMPARE(str(d18, MemOperand(x19, 8, PostIndex)), "st in TEST()
[all...]
H A Dtest-cpu-features-aarch64.cc287 TEST_NONE(ldpsw_1, ldpsw(x0, x1, MemOperand(x2, -36, PostIndex)))
290 TEST_NONE(ldp_1, ldp(w0, w1, MemOperand(x2, -212, PostIndex)))
293 TEST_NONE(ldp_4, ldp(x0, x1, MemOperand(x2, 8, PostIndex)))
295 TEST_NONE(ldrb_0, ldrb(w0, MemOperand(x1, -219, PostIndex)))
301 TEST_NONE(ldrh_0, ldrh(w0, MemOperand(x1, -135, PostIndex)))
306 TEST_NONE(ldrsb_0, ldrsb(w0, MemOperand(x1, 160, PostIndex)))
309 TEST_NONE(ldrsb_3, ldrsb(x0, MemOperand(x1, 33, PostIndex)))
318 TEST_NONE(ldrsh_0, ldrsh(w0, MemOperand(x1, 11, PostIndex)))
321 TEST_NONE(ldrsh_3, ldrsh(x0, MemOperand(x1, -78, PostIndex)))
328 TEST_NONE(ldrsw_0, ldrsw(x0, MemOperand(x1, 73, PostIndex)))
[all...]
H A Dtest-assembler-neon-aarch64.cc63 __ Str(b0, MemOperand(x18, sizeof(dst[0]), PostIndex)); in TEST()
64 __ Ldr(b1, MemOperand(x19, sizeof(src[0]), PostIndex)); in TEST()
105 __ Str(h0, MemOperand(x18, sizeof(dst[0]), PostIndex)); in TEST()
106 __ Ldr(h1, MemOperand(x19, sizeof(src[0]), PostIndex)); in TEST()
152 __ Str(q0, MemOperand(x18, 16, PostIndex)); in TEST()
153 __ Ldr(q1, MemOperand(x19, 16, PostIndex)); in TEST()
279 __ Ldp(q31, q0, MemOperand(x16, 4 * sizeof(src[0]), PostIndex)); in TEST()
367 __ Ld1(v2.V8B(), MemOperand(x17, x23, PostIndex)); in TEST()
368 __ Ld1(v3.V8B(), v4.V8B(), MemOperand(x18, 16, PostIndex)); in TEST()
369 __ Ld1(v5.V4H(), v6.V4H(), v7.V4H(), MemOperand(x19, 24, PostIndex)); in TEST()
[all...]
H A Dtest-disasm-aarch64.cc983 COMPARE(st2g(x22, MemOperand(x24, 1600, PostIndex)), in TEST()
988 COMPARE(stg(x4, MemOperand(sp, -256, PostIndex)), "stg x4, [sp], #-256"); in TEST()
993 COMPARE(stgp(x5, x21, MemOperand(sp, 1008, PostIndex)), in TEST()
998 COMPARE(stzg(x5, MemOperand(sp, -2560, PostIndex)), "stzg x5, [sp], #-2560"); in TEST()
1002 COMPARE(stz2g(sp, MemOperand(x7, -256, PostIndex)), "stz2g sp, [x7], #-256"); in TEST()
1010 COMPARE_MACRO(St2g(x18, MemOperand(x2, 352, PostIndex)), in TEST()
1016 COMPARE_MACRO(Stg(x14, MemOperand(x20, 1024, PostIndex)), in TEST()
1022 COMPARE_MACRO(Stgp(x14, x16, MemOperand(x0, 576, PostIndex)), in TEST()
1028 COMPARE_MACRO(Stz2g(sp, MemOperand(sp, 1024, PostIndex)), in TEST()
1034 COMPARE_MACRO(Stzg(x8, MemOperand(x3, 1488, PostIndex)), in TEST()
[all...]
H A Dtest-assembler-aarch64.cc2978 case PostIndex:
3030 case PostIndex:
3087 MTEStoreTagHelper(&MacroAssembler::St2g, PostIndex, StgPairTag);
3093 MTEStoreTagHelper(&MacroAssembler::Stg, PostIndex);
3099 MTEStoreTagHelper(&MacroAssembler::Stz2g, PostIndex, StgPairTag | StgZeroing);
3105 MTEStoreTagHelper(&MacroAssembler::Stzg, PostIndex, StgZeroing);
3205 __ Stgp(x7, x8, MemOperand(base, offset, PostIndex));
3212 __ Stgp(x8, x9, MemOperand(base, offset, PostIndex));
3219 __ Stgp(x9, x10, MemOperand(base, offset, PostIndex));
3321 __ Ldr(w1, MemOperand(x24, 4096 * sizeof(src[0]), PostIndex));
[all...]
/third_party/vixl/examples/aarch64/
H A Dadd2-vectors.cc60 __ Ld1(v1.V16B(), MemOperand(x1, 16, PostIndex)); in GenerateAdd2Vectors()
62 __ St1(v0.V16B(), MemOperand(x0, 16, PostIndex)); in GenerateAdd2Vectors()
75 __ Ldrb(w6, MemOperand(x1, 1, PostIndex)); in GenerateAdd2Vectors()
77 __ Strb(w5, MemOperand(x0, 1, PostIndex)); in GenerateAdd2Vectors()
H A Dcrc-checksums.cc60 __ Ldrb(w3, MemOperand(x2, 1, PostIndex)); in GenerateCrc32()
H A Dsum-array.cc52 __ Ldrb(w3, MemOperand(x2, 1, PostIndex)); // w3 = *(x2++) in GenerateSumArray()
/third_party/node/deps/v8/src/regexp/arm64/
H A Dregexp-macro-assembler-arm64.cc278 __ Ldrb(w10, MemOperand(characters_address, 1, PostIndex)); in CheckCharacters()
281 __ Ldrh(w10, MemOperand(characters_address, 2, PostIndex)); in CheckCharacters()
369 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); in CheckNotBackReferenceIgnoreCase()
370 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); in CheckNotBackReferenceIgnoreCase()
513 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); in CheckNotBackReference()
514 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); in CheckNotBackReference()
517 __ Ldrh(w10, MemOperand(capture_start_address, 2, PostIndex)); in CheckNotBackReference()
518 __ Ldrh(w11, MemOperand(current_position_address, 2, PostIndex)); in CheckNotBackReference()
995 MemOperand(output_array(), kSystemPointerSize, PostIndex)); in GetCode()
1015 MemOperand(base, -kSystemPointerSize, PostIndex)); in GetCode()
[all...]
/third_party/node/deps/v8/src/codegen/arm/
H A Dmacro-assembler-arm.h183 ldr(src2, MemOperand(sp, 4, PostIndex), cond); in Pop()
184 ldr(src1, MemOperand(sp, 4, PostIndex), cond); in Pop()
195 ldr(src3, MemOperand(sp, 4, PostIndex), cond); in Pop()
200 ldr(src1, MemOperand(sp, 4, PostIndex), cond); in Pop()
213 ldr(src4, MemOperand(sp, 4, PostIndex), cond); in Pop()
222 ldr(src1, MemOperand(sp, 4, PostIndex), cond); in Pop()
/third_party/node/deps/v8/src/regexp/arm/
H A Dregexp-macro-assembler-arm.cc270 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); in CheckNotBackReferenceIgnoreCase()
271 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); in CheckNotBackReferenceIgnoreCase()
398 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); in CheckNotBackReference()
399 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); in CheckNotBackReference()
402 __ ldrh(r3, MemOperand(r0, char_size(), PostIndex)); in CheckNotBackReference()
403 __ ldrh(r4, MemOperand(r2, char_size(), PostIndex)); in CheckNotBackReference()
855 __ str(r2, MemOperand(r0, kPointerSize, PostIndex)); in GetCode()
856 __ str(r3, MemOperand(r0, kPointerSize, PostIndex)); in GetCode()
1275 MemOperand(backtrack_stackpointer(), kPointerSize, PostIndex));
/third_party/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.cc1792 case PostIndex: in Delegate()
1806 MemOperand(rn, load_store_offset, PostIndex)); in Delegate()
1889 case PostIndex: in Delegate()
2018 case PostIndex: in Delegate()
2032 MemOperand(rn, load_store_offset, PostIndex)); in Delegate()
2065 case PostIndex: in Delegate()
2165 case PostIndex: in Delegate()
2238 case PostIndex: in Delegate()
H A Doperands-aarch32.cc520 if (operand.GetAddrMode() == PostIndex) { in operator <<()
552 if (operand.GetAddrMode() == PostIndex) { in operator <<()

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