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Searched refs:PKT3_SET_CONTEXT_REG (Results 1 - 12 of 12) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h146 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
162 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
H A Deg_debug.c162 if (op == PKT3_SET_CONTEXT_REG || in ac_parse_packet3()
177 case PKT3_SET_CONTEXT_REG: in ac_parse_packet3()
H A Dr600d_common.h80 #define PKT3_SET_CONTEXT_REG 0x69 macro
H A Dr600_pipe.h870 #define PKT3_SET_CONTEXT_REG 0x69 macro
919 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; in r600_store_context_reg_seq()
H A Devergreend.h105 #define PKT3_SET_CONTEXT_REG 0x69 macro
H A Dr600d.h113 #define PKT3_SET_CONTEXT_REG 0x69 macro
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h65 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
81 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
H A Dradv_device_generated_commands.c83 /* One PKT3_SET_CONTEXT_REG (PA_SU_SC_MODE_CNTL) */ in radv_get_sequence_size()
742 nir_imm_int(&b, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)), in build_dgc_prepare_shader()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_pm4.c92 opcode = PKT3_SET_CONTEXT_REG; in si_pm4_set_reg()
H A Dsi_build_pm4.h91 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
108 radeon_emit(PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
167 /* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
/third_party/mesa3d/src/amd/common/
H A Dsid.h239 #define PKT3_SET_CONTEXT_REG 0x69 macro
H A Dac_debug.c275 if (op == PKT3_SET_CONTEXT_REG || op == PKT3_SET_CONFIG_REG || op == PKT3_SET_UCONFIG_REG || in ac_parse_packet3()
285 case PKT3_SET_CONTEXT_REG: in ac_parse_packet3()

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