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Searched refs:Orrs (Results 1 - 13 of 13) sorted by relevance

/third_party/vixl/test/aarch32/
H A Dtest-simulator-cond-rd-rn-operand-rm-a32.cc127 M(Orrs) \
H A Dtest-simulator-cond-rd-rn-operand-rm-t32.cc129 M(Orrs) \
H A Dtest-simulator-cond-rd-rn-operand-const-a32.cc127 M(Orrs) \
H A Dtest-simulator-cond-rd-rn-operand-const-t32.cc129 M(Orrs) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc127 M(Orrs) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc129 M(Orrs) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc127 M(Orrs) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc129 M(Orrs) \
H A Dtest-disasm-a32.cc1514 COMPARE_T32(Orrs(r0, r1, 0x00ffffff), "orns r0, r1, #0xff000000\n"); in TEST()
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc127 M(Orrs) \
H A Dtest-assembler-aarch32.cc3301 __ Orrs(r0, r0, 0); in TEST()
6121 // CHECK_SIZE_MATCH(Orrs(r7, r7, r6),
6122 // Orrs(r7, r6, r7));
6124 // CHECK_SIZE_MATCH(Orrs(eq, r7, r7, r6),
6125 // Orrs(eq, r7, r6, r7));
/third_party/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.h3264 Orrs(cond, rd, rn, operand); in MacroAssembler()
3275 Orrs(cond, rd, rn, operand); in MacroAssembler()
3289 void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
3303 void Orrs(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
3304 Orrs(al, rd, rn, operand); in MacroAssembler()
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.h5648 void Orrs(const PRegisterWithLaneSize& pd, in Orrs() function in vixl::aarch64::MacroAssembler

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