| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 75 __ Orr(w10, w0, 0xffffff1); in TEST()
89 __ Orr(sp, x0, 0x1f7de); in TEST()
140 __ Orr(sp, xzr, 0x1fff); in TEST()
144 __ Orr(wsp, wzr, 0xfffffff8); in TEST()
148 __ Orr(sp, xzr, 0xfffffff8); in TEST()
153 __ Orr(wsp, w5, 0x1234); in TEST()
462 __ Orr(x2, x0, Operand(x1)); in TEST()
463 __ Orr(w3, w0, Operand(w1, LSL, 28)); in TEST()
464 __ Orr(x4, x0, Operand(x1, LSL, 32)); in TEST()
465 __ Orr(x in TEST()
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| H A D | test-disasm-neon-aarch64.cc | 1761 COMPARE_MACRO(Orr(v6.V8B(), v7.V8B(), v8.V8B()), "orr v6.8b, v7.8b, v8.8b"); in TEST()
1762 COMPARE_MACRO(Orr(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
1765 COMPARE_MACRO(Orr(v6.V8B(), v7.V8B(), v7.V8B()), "mov v6.8b, v7.8b"); in TEST()
1766 COMPARE_MACRO(Orr(v6.V16B(), v7.V16B(), v7.V16B()), "mov v6.16b, v7.16b"); in TEST()
3153 COMPARE_MACRO(Orr(v4.V4H(), 0xaa, 0), "orr v4.4h, #0xaa, lsl #0"); in TEST()
3154 COMPARE_MACRO(Orr(v1.V8H(), 0xcc, 8), "orr v1.8h, #0xcc, lsl #8"); in TEST()
3155 COMPARE_MACRO(Orr(v4.V2S(), 0xaa, 0), "orr v4.2s, #0xaa, lsl #0"); in TEST()
3156 COMPARE_MACRO(Orr(v1.V2S(), 0xcc, 8), "orr v1.2s, #0xcc, lsl #8"); in TEST()
3157 COMPARE_MACRO(Orr(v4.V4S(), 0xaa, 16), "orr v4.4s, #0xaa, lsl #16"); in TEST()
3158 COMPARE_MACRO(Orr(v in TEST()
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| H A D | test-disasm-aarch64.cc | 2906 COMPARE_MACRO(Orr(w2, w3, 0), "mov w2, w3"); in TEST()
2907 COMPARE_MACRO(Orr(x2, x3, 0), "mov x2, x3"); in TEST()
2920 COMPARE_MACRO(Orr(w14, w15, 0xffffffff), "mov w14, #0xffffffff"); in TEST()
2921 COMPARE_MACRO(Orr(x14, x15, 0xffffffff), "orr x14, x15, #0xffffffff"); in TEST()
2922 COMPARE_MACRO(Orr(x14, x15, 0xffffffffffffffff), in TEST()
2938 COMPARE_MACRO(Orr(wsp, w5, 0x1234), in TEST()
2942 COMPARE_MACRO(Orr(sp, x15, 0x123), in TEST()
2963 COMPARE_MACRO(Orr(x0, x1, 0x4242), in TEST()
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| H A D | test-assembler-neon-aarch64.cc | 6071 __ Orr(v16.V16B(), v0.V16B(), v0.V16B()); // self test in TEST()
6072 __ Orr(v17.V16B(), v0.V16B(), v1.V16B()); // all combinations in TEST()
6073 __ Orr(v24.V8B(), v0.V8B(), v0.V8B()); // self test in TEST()
6074 __ Orr(v25.V8B(), v0.V8B(), v1.V8B()); // all combinations in TEST()
7646 __ Orr(v16.V4H(), 0x00, 0); in TEST()
7647 __ Orr(v17.V4H(), 0xff, 8); in TEST()
7648 __ Orr(v18.V8H(), 0x00, 0); in TEST()
7649 __ Orr(v19.V8H(), 0xff, 8); in TEST()
7651 __ Orr(v20.V2S(), 0x00, 0); in TEST()
7652 __ Orr(v2 in TEST()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 1502 COMPARE_BOTH(Orr(r0, r1, 0xffffffff), "mvn r0, #0\n"); in TEST()
1503 COMPARE_BOTH(Orr(r0, r0, 0), ""); in TEST()
1511 // Special case for Orr <-> Orn correspondence. in TEST()
1513 COMPARE_T32(Orr(r0, r1, 0x00ffffff), "orn r0, r1, #0xff000000\n"); in TEST()
3541 COMPARE_T32(Orr(eq, r0, r0, r1), in TEST()
3545 COMPARE_T32(Orr(eq, r0, r1, r2), in TEST()
4171 CHECK_T32_16(Orr(DontCare, r7, r7, r6), "orrs r7, r6\n"); in TEST()
4173 CHECK_T32_16_IT_BLOCK(Orr(DontCare, eq, r7, r7, r6), in TEST()
4255 COMPARE_BOTH(Orr(r0, r0, r0), ""); in TEST()
4256 COMPARE_BOTH(Orr(DontCar in TEST()
[all...] |
| H A D | test-simulator-cond-rd-operand-const-a32.cc | 522 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-operand-imm16-t32.cc | 475 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-rm-ge-a32.cc | 476 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
488 __ Orr(q_bit, q_bit, saved_nzcv_bits); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-rm-ge-t32.cc | 476 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
488 __ Orr(q_bit, q_bit, saved_nzcv_bits); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-rm-q-a32.cc | 460 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
472 __ Orr(q_bit, q_bit, saved_nzcv_bits); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-rm-q-t32.cc | 460 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
472 __ Orr(q_bit, q_bit, saved_nzcv_bits); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-rm-sel-a32.cc | 453 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
465 __ Orr(q_bit, q_bit, saved_nzcv_bits); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-rm-sel-t32.cc | 453 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
465 __ Orr(q_bit, q_bit, saved_nzcv_bits); in TestHelper()
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| H A D | test-simulator-cond-rd-operand-const-t32.cc | 637 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-operand-rn-a32.cc | 559 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-operand-rn-t32.cc | 559 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 126 M(Orr) \
1158 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 128 M(Orr) \
1158 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-operand-const-a32.cc | 126 M(Orr) \
1157 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 128 M(Orr) \
1181 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 126 M(Orr) \
1477 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit); in TestHelper()
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| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 222 __ Orr(PickR(size), PickR(size), Operand(PickR(size))); in GenerateOperandSequence()
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| /third_party/node/deps/v8/src/regexp/arm64/ |
| H A D | regexp-macro-assembler-arm64.cc | 375 __ Orr(w10, w10, 0x20); // Convert capture character to lower-case. in CheckNotBackReferenceIgnoreCase()
376 __ Orr(w11, w11, 0x20); // Also convert input character. in CheckNotBackReferenceIgnoreCase()
912 __ Orr(twice_non_position_value(), string_start_minus_one().X(), in GetCode()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 392 V(orr, Orr) \
667 inline void Orr(const Register& rd, const Register& rn,
669 void Orr(const VRegister& vd, const int imm8, const int left_shift = 0) { in Orr() function in v8::internal::TurboAssembler
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 407 Orr, enumerator
1011 using InstARM32Orr = InstARM32ThreeAddrGPR<InstARM32::Orr>;
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