Searched refs:NVC0C0_QMDV02_01_VAL_SET (Results 1 - 1 of 1) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| H A D | nve4_compute.c | 38 #define NVC0C0_QMDV02_01_VAL_SET(p,a...) NVVAL_MW_SET((p), NVC0C0, QMDV02_01, ##a) macro
578 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address); in gp100_cp_launch_desc_set_cb()
579 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32); in gp100_cp_launch_desc_set_cb()
580 NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_SIZE_SHIFTED4, index, in gp100_cp_launch_desc_set_cb()
696 NVC0C0_QMDV02_01_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1); in gp100_compute_setup_launch_desc()
701 NVC0C0_QMDV02_01_VAL_SET(qmd, PROGRAM_OFFSET, cp->code_base); in gp100_compute_setup_launch_desc()
703 NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]); in gp100_compute_setup_launch_desc()
704 NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]); in gp100_compute_setup_launch_desc()
705 NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_DEPTH, info->grid[2]); in gp100_compute_setup_launch_desc()
706 NVC0C0_QMDV02_01_VAL_SET(qm in gp100_compute_setup_launch_desc()
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