| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_opt_value_numbering.cpp | 107 case Format::MIMG: return hash_murmur_32<MIMG_instruction>(instr); in operator ()()
267 case Format::MIMG: { in operator ()()
349 case Format::MIMG: in can_eliminate()
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| H A D | aco_opcodes.py | 63 MIMG = 11 variable in Format
119 elif self == Format.MIMG:
1414 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1416 opcode("image_msaa_load", -1, -1, 0x80, Format.MIMG, InstrClass.VMem) #GFX10.3+
1440 opcode(name, gfx7, gfx89, gfx7, Format.MIMG, InstrClass.VMem, is_atomic = True)
1486 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1501 opcode(name, -1, -1, code, Format.MIMG, InstrClass.VMem)
1534 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1536 opcode("image_bvh64_intersect_ray", -1, -1, 231, Format.MIMG, InstrClass.VMem)
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| H A D | aco_insert_waitcnt.cpp | 686 case Format::MIMG: in gen()
696 if (ctx.gfx_level == GFX6 && instr->format != Format::MIMG && instr->operands.size() == 4) { in gen()
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| H A D | aco_register_allocation.cpp | 1555 unsigned first_operand = vec->format == Format::MIMG ? 3 : 0; in get_reg_vector()
1565 if (vec->format != Format::MIMG || is_mimg_vaddr_intact(ctx, reg_file, vec)) { in get_reg_vector()
1580 /* return if MIMG vaddr components don't remain vector-aligned */ in get_reg_vector()
1581 if (vec->format == Format::MIMG) in get_reg_vector()
2389 } else if (instr->format == Format::MIMG && instr->operands.size() > 4) { in get_affinities()
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| H A D | aco_ir.h | 84 MIMG = 11, member in aco::Format
1159 constexpr bool isMIMG() const noexcept { return format == Format::MIMG; }
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| H A D | aco_assembler.cpp | 450 case Format::MIMG: { in emit_instruction()
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| H A D | aco_ir.cpp | 192 case Format::MIMG: return instr->mimg().sync; in get_sync_info()
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| H A D | aco_print_ir.cpp | 391 case Format::MIMG: { in print_instr_format_specific()
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| H A D | aco_validate.cpp | 610 case Format::MIMG: { in validate_ir()
611 check(instr->operands.size() >= 4, "MIMG instructions must have at least 4 operands", in validate_ir()
615 "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get()); in validate_ir()
618 "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get()); in validate_ir()
625 "MIMG operands[2] (VDATA) must be the same as definitions[0] for atomics and " in validate_ir()
635 "MIMG operands[3] (VADDR) must be VGPR", instr.get()); in validate_ir()
637 check(instr->operands[i].regClass() == v1, "MIMG VADDR must be v1 if NSA is used", in validate_ir()
645 "MIMG definitions[0] (VDATA) must be VGPR", instr.get()); in validate_ir()
647 "Only D16 MIMG instructions can load subdword values.", instr.get()); in validate_ir()
649 "D16 MIMG instruction in validate_ir()
[all...] |
| H A D | aco_instruction_selection.cpp | 6066 create_instruction<MIMG_instruction>(op, Format::MIMG, 3 + coords.size(), dst.isTemp())};
9836 /* gather MIMG address components */
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 101 MIMG, enumerator
336 return MIMG; in getInstClass()
496 if (InstClass == MIMG) { in setMI()
510 } else if (InstClass != MIMG) { in setMI()
662 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()
724 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()
912 // Check both offsets (or masks for MIMG) can be combined and fit in the in findMatchingInst()
915 CI.InstClass == MIMG in findMatchingInst()
1439 case MIMG: in getNewOpcode()
1452 if (CI.InstClass == MIMG) { in getSubRegIdxs()
[all...] |
| H A D | SIDefines.h | 48 MIMG = 1 << 19,
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| H A D | SIInstrInfo.h | 482 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
486 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| /third_party/mesa3d/src/amd/compiler/tests/ |
| H A D | test_insert_nops.cpp | 37 aco_opcode::image_sample, Format::MIMG, 3 + addrs, 1)}; in create_mimg()
73 /* no nop needed because the MIMG is not NSA */
130 /* no nop needed because the MIMG is not NSA */
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| H A D | test_hard_clause.cpp | 71 aco_opcode::image_sample, Format::MIMG, 5, 1)}; in create_mimg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 294 if (AMDGPU::isGFX10(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 373 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { in getInstruction()
460 // Note that before gfx10, the MIMG encoding provided no information about
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2946 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGDataSize()
2978 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 || !isGFX10()) in validateMIMGAddrSize()
3019 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGAtomicDMask()
3046 // other MIMG instructions. The only useful DMASK values are in validateMIMGGatherDMask()
3093 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGD16()
3109 if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0) in validateMIMGDim()
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