| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 518 MFLO = 1, enumerator
1122 return Latency::DIV + Latency::MFLO; in DivLatency()
1128 return 1 + Latency::DIV + Latency::MFLO; in DivLatency()
1138 return Latency::DIVU + Latency::MFLO; in DivuLatency()
1144 return 1 + Latency::DIVU + Latency::MFLO; in DivuLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 545 MFLO = 1, enumerator
595 latency = Latency::DMULT + Latency::MFLO; in DmulLatency()
663 latency = Latency::DDIV + Latency::MFLO; in DdivLatency()
676 latency = Latency::DDIVU + Latency::MFLO; in DdivuLatency()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; in copyPhysReg()
305 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
424 expandPseudoMFHiLo(MBB, MI, Mips::MFLO); in expandPostRAPseudo()
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| H A D | MipsISelLowering.h | 128 MFLO,
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| H A D | MipsSEFrameLowering.cpp | 822 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
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| H A D | MipsSEISelLowering.cpp | 1276 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); in lowerMulDiv()
1296 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); in extractLOHI()
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| H A D | MipsFastISel.cpp | 1955 : Mips::MFLO; in selectDivRem()
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| H A D | MipsISelLowering.cpp | 205 case MipsISD::MFLO: return "MipsISD::MFLO"; in getTargetNodeName()
584 // insert MFLO in performDivRemCombine()
1049 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in performMADD_MSUBCombine()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 240 #define MFLO (HI(0) | LO(18)) macro
1843 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
1847 return push_inst(compiler, MFLO | D(dst), DR(dst)); in emit_single_op()
1857 FAIL_IF(push_inst(compiler, MFLO | D(dst), DR(dst))); in emit_single_op()
2183 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
2220 FAIL_IF(push_inst(compiler, MFLO | D(SLJIT_R0), DR(SLJIT_R0))); in sljit_emit_op0()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 525 MFLO = ((2U << 3) + 2),
1329 // On r6, DCLZ_R6 aliases to existing MFLO.
1341 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| H A D | assembler-mips64.cc | 2431 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO); in mflo()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 528 MFLO = ((2U << 3) + 2),
1283 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| H A D | assembler-mips.cc | 2292 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO); in mflo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4214 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4263 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4301 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
5062 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5082 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5104 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5125 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5153 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3897 case MFLO: // MFLO == DCLZ on R6. in DecodeTypeRegisterSPECIAL()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3887 case MFLO: in DecodeTypeRegisterSPECIAL()
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