| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 544 MFHI = 1, enumerator
608 latency = Latency::MULT + Latency::MFHI; in MulhLatency()
621 latency = Latency::MULTU + Latency::MFHI; in MulhuLatency()
634 latency = Latency::DMULT + Latency::MFHI; in DMulhLatency()
689 latency = Latency::DIV + Latency::MFHI; in ModLatency()
702 latency = Latency::DIVU + Latency::MFHI; in ModuLatency()
715 latency = Latency::DDIV + Latency::MFHI; in DmodLatency()
728 latency = Latency::DDIV + Latency::MFHI; in DmoduLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 517 MFHI = 1, enumerator
1066 return Latency::MULT + Latency::MFHI; in MulhLatency()
1072 return 1 + Latency::MULT + Latency::MFHI; in MulhLatency()
1082 return Latency::MULTU + Latency::MFHI; in MulhuLatency()
1088 return 1 + Latency::MULTU + Latency::MFHI; in MulhuLatency()
1102 return Latency::DIV + Latency::MFHI; in ModLatency()
1108 return 1 + Latency::DIV + Latency::MFHI; in ModLatency()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
299 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
418 expandPseudoMFHiLo(MBB, MI, Mips::MFHI); in expandPostRAPseudo()
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| H A D | MipsISelLowering.h | 127 MFHI,
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| H A D | MipsSEFrameLowering.cpp | 822 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
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| H A D | MipsSEISelLowering.cpp | 1278 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); in lowerMulDiv()
1297 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); in extractLOHI()
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| H A D | MipsFastISel.cpp | 1954 ? Mips::MFHI in selectDivRem()
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| H A D | MipsISelLowering.cpp | 204 case MipsISD::MFHI: return "MipsISD::MFHI"; in getTargetNodeName()
593 // insert MFHI in performDivRemCombine()
1050 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in performMADD_MSUBCombine()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 522 MFHI = ((2U << 3) + 0),
1341 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| H A D | assembler-mips64.cc | 2427 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI); in mfhi()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 525 MFHI = ((2U << 3) + 0),
1283 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
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| H A D | assembler-mips.cc | 2288 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI); in mfhi()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 239 #define MFHI (HI(0) | LO(16)) macro
1856 FAIL_IF(push_inst(compiler, MFHI | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
2184 return push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)); in sljit_emit_op0()
2221 return (op >= SLJIT_DIV_UW) ? SLJIT_SUCCESS : push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)); in sljit_emit_op0()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4214 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4263 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4301 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
5087 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
5124 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3885 case MFHI: // MFHI == CLZ on R6. in DecodeTypeRegisterSPECIAL()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3875 case MFHI: // MFHI == CLZ on R6. in DecodeTypeRegisterSPECIAL()
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