Searched refs:LWC1 (Results 1 - 14 of 14) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 509 LWC1 = 4, enumerator
923 return Latency::LWC1; in Ulwc1Latency()
938 int latency = AdjustBaseAndOffsetLatency() + Latency::LWC1; in Ldc1Latency()
940 return latency + Latency::LWC1; in Ldc1Latency()
1674 return Latency::LWC1; in GetInstructionLatency()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 225 case Mips::LWC1: in isBasePlusOffsetMemoryAccess()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 538 LWC1 = 4, enumerator
883 int Lwc1Latency() { return AdjustBaseAndOffsetLatency() + Latency::LWC1; } in Lwc1Latency()
1686 latency = Latency::LWC1; in GetInstructionLatency()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
345 Opc = Mips::LWC1; in loadRegFromStack()
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| H A D | MipsInstructionSelector.cpp | 222 return isStore ? Mips::SWC1 : Mips::LWC1; in selectLoadStoreOpCode()
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| H A D | MipsFastISel.cpp | 780 Opc = Mips::LWC1; in emitLoad()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 475 LWC1 = ((6U << 3) + 1) << kOpcodeShift,
1322 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
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| H A D | assembler-mips64.cc | 2663 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_); in lwc1()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 482 LWC1 = ((6U << 3) + 1) << kOpcodeShift,
1270 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
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| H A D | assembler-mips.cc | 2402 GenInstrImmediate(LWC1, tmp.rm(), fd, tmp.offset()); in lwc1()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 233 #define LWC1 (HI(49)) macro
938 FAIL_IF(push_inst(compiler, LWC1 | base | FT(float_arg_count) | IMM(local_size + (arg_count << 2)), MOVABLE_INS)); in sljit_emit_enter()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 7124 case LWC1:
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 6746 case LWC1:
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3395 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
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