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Searched refs:IsSignallingNaN (Results 1 - 10 of 10) sorted by relevance

/third_party/node/deps/v8/src/codegen/arm64/
H A Dutils-arm64.h72 inline bool IsSignallingNaN(double num) { in IsSignallingNaN() function
80 inline bool IsSignallingNaN(float num) { in IsSignallingNaN() function
88 inline bool IsSignallingNaN(float16 num) { in IsSignallingNaN() function
95 return std::isnan(num) && !IsSignallingNaN(num); in IsQuietNaN()
/third_party/vixl/src/
H A Dutils-vixl.cc300 if (IsSignallingNaN(value)) { in FPToFloat()
345 if (IsSignallingNaN(value)) { in FPToFloat()
408 if (IsSignallingNaN(value)) { in FPToDouble()
462 if (IsSignallingNaN(value)) { in FPToFloat16()
517 if (IsSignallingNaN(value)) { in FPToFloat16()
H A Dutils-vixl.h579 inline bool IsSignallingNaN(double num) { in IsSignallingNaN() function
589 inline bool IsSignallingNaN(float num) { in IsSignallingNaN() function
599 inline bool IsSignallingNaN(Float16 num) { in IsSignallingNaN() function
607 return IsNaN(num) && !IsSignallingNaN(num); in IsQuietNaN()
/third_party/vixl/test/aarch64/
H A Dtest-assembler-fp-aarch64.cc913 VIXL_ASSERT(IsSignallingNaN(sig1)); in TEST()
914 VIXL_ASSERT(IsSignallingNaN(sig2)); in TEST()
915 VIXL_ASSERT(IsSignallingNaN(siga)); in TEST()
1125 VIXL_ASSERT(IsSignallingNaN(sig1)); in TEST()
1126 VIXL_ASSERT(IsSignallingNaN(sig2)); in TEST()
1127 VIXL_ASSERT(IsSignallingNaN(siga)); in TEST()
1534 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
1638 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
4918 VIXL_ASSERT(IsSignallingNaN(sn));
4994 VIXL_ASSERT(IsSignallingNaN(s
[all...]
H A Dtest-assembler-sve-aarch64.cc17224 VIXL_ASSERT(IsSignallingNaN(sa));
17225 VIXL_ASSERT(IsSignallingNaN(sn));
17226 VIXL_ASSERT(IsSignallingNaN(sm));
17380 VIXL_ASSERT(IsSignallingNaN(sa));
17381 VIXL_ASSERT(IsSignallingNaN(sn));
17382 VIXL_ASSERT(IsSignallingNaN(sm));
17536 VIXL_ASSERT(IsSignallingNaN(sa));
17537 VIXL_ASSERT(IsSignallingNaN(sn));
17538 VIXL_ASSERT(IsSignallingNaN(sm));
H A Dtest-assembler-neon-aarch64.cc10629 if (IsSignallingNaN(n)) { in MinMaxHelper()
10632 } else if (IsSignallingNaN(m)) { in MinMaxHelper()
10673 VIXL_ASSERT(IsSignallingNaN(snan)); in TEST()
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.h2479 if (IsSignallingNaN(op1)) { in FPProcessNaNs()
2481 } else if (IsSignallingNaN(op2)) { in FPProcessNaNs()
2496 if (IsSignallingNaN(op1)) { in FPProcessNaNs3()
2498 } else if (IsSignallingNaN(op2)) { in FPProcessNaNs3()
2500 } else if (IsSignallingNaN(op3)) { in FPProcessNaNs3()
H A Dsimulator-logic-arm64.cc94 if (IsSignallingNaN(value)) { in FPToDouble()
163 if (IsSignallingNaN(value)) { in FPToFloat()
208 if (IsSignallingNaN(value)) { in FPToFloat16()
256 if (IsSignallingNaN(value)) { in FPToFloat16()
299 if (IsSignallingNaN(value)) { in FPToFloat()
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.h5193 if (IsSignallingNaN(op)) {
5201 if (IsSignallingNaN(op1)) {
5203 } else if (IsSignallingNaN(op2)) {
5218 if (IsSignallingNaN(op1)) {
5220 } else if (IsSignallingNaN(op2)) {
5222 } else if (IsSignallingNaN(op3)) {
H A Dsimulator-aarch64.cc599 VIXL_ASSERT(IsSignallingNaN(RawbitsToDouble(nan_bits & kDRegMask))); in Simulator()
600 VIXL_ASSERT(IsSignallingNaN(RawbitsToFloat(nan_bits & kSRegMask))); in Simulator()
1115 if (IsSignallingNaN(val0) || IsSignallingNaN(val1) || in Simulator()

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