Searched refs:IsLaneSizeD (Results 1 - 7 of 7) sorted by relevance
| /third_party/vixl/src/aarch64/ |
| H A D | assembler-sve-aarch64.cc | 134 VIXL_ASSERT(zd.IsLaneSizeD()); in and_()
143 VIXL_ASSERT(zd.IsLaneSizeD()); in bic()
152 VIXL_ASSERT(zd.IsLaneSizeD()); in eor()
161 VIXL_ASSERT(zd.IsLaneSizeD()); in orr()
2458 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in sdiv()
2475 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in sdivr()
2588 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in udiv()
2605 VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD()); in udivr()
2977 VIXL_ASSERT(zm.IsLaneSizeD()); in cmpeq()
2994 VIXL_ASSERT(zm.IsLaneSizeD()); in cmpge()
[all...] |
| H A D | operands-aarch64.h | 617 (regoffset_.IsLaneSizeS() || regoffset_.IsLaneSizeD()) && !IsMulVl(); in IsScalarPlusVector()
622 (base_.IsLaneSizeS() || base_.IsLaneSizeD()) && in IsVectorPlusImmediate()
628 (base_.IsLaneSizeS() || base_.IsLaneSizeD()); in IsVectorPlusScalar()
634 (base_.IsLaneSizeS() || base_.IsLaneSizeD()); in IsVectorPlusVector()
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| H A D | assembler-aarch64.cc | 4177 V(shadd, NEON_SHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
4178 V(uhadd, NEON_UHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
4179 V(srhadd, NEON_SRHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
4180 V(urhadd, NEON_URHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
4181 V(shsub, NEON_SHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
4182 V(uhsub, NEON_UHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
4183 V(smax, NEON_SMAX, vd.IsVector() && !vd.IsLaneSizeD()) \
4184 V(smaxp, NEON_SMAXP, vd.IsVector() && !vd.IsLaneSizeD()) \
4185 V(smin, NEON_SMIN, vd.IsVector() && !vd.IsLaneSizeD()) \
4186 V(sminp, NEON_SMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
[all...] |
| H A D | registers-aarch64.h | 171 bool IsLaneSizeD() const { return lane_size_ == kEncodedDRegSize; }
370 bool Is2D() const { return IsQ() && IsLaneSizeD(); }
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| H A D | macro-assembler-aarch64.h | 6670 VIXL_ASSERT(zn.IsLaneSizeD()); in Fcvtx()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 3073 V(shadd, NEON_SHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3074 V(uhadd, NEON_UHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3075 V(srhadd, NEON_SRHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3076 V(urhadd, NEON_URHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3077 V(shsub, NEON_SHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
3078 V(uhsub, NEON_UHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
3079 V(smax, NEON_SMAX, vd.IsVector() && !vd.IsLaneSizeD()) \
3080 V(smaxp, NEON_SMAXP, vd.IsVector() && !vd.IsLaneSizeD()) \
3081 V(smin, NEON_SMIN, vd.IsVector() && !vd.IsLaneSizeD()) \
3082 V(sminp, NEON_SMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
[all...] |
| H A D | register-arm64.h | 399 bool IsLaneSizeD() const { return LaneSizeInBits() == kDRegSizeInBits; } in IsLaneSizeD() function in v8::internal::VRegister
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