Searched refs:Is2S (Results 1 - 7 of 7) sorted by relevance
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1438 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) || in NEON3DifferentL()
1454 (vm.Is2S() && vd.Is2D()) || (vm.Is16B() && vd.Is8H()) || in NEON3DifferentW()
1463 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEON3DifferentHN()
1499 V(sqdmlal, NEON_SQDMLAL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1501 V(sqdmlsl, NEON_SQDMLSL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1503 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1607 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) || in NEONShiftImmediateL()
1628 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) || in NEONShiftImmediateN()
1976 DCHECK(vd.Is2S() || vd.Is4S()); in ursqrte()
1982 DCHECK(vd.Is2S() || v in urecpe()
[all...] |
| H A D | register-arm64.h | 375 bool Is2S() const { return (Is64Bits() && (lane_count_ == 2)); } in Is2S() function in v8::internal::VRegister
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| H A D | macro-assembler-arm64-inl.h | 665 if (vd.Is1S() || vd.Is2S() || vd.Is4S()) { in Fmov()
697 DCHECK(vd.Is1S() || vd.Is2S() || vd.Is4S()); in Fmov()
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| H A D | macro-assembler-arm64.cc | 558 } else if (vd.Is2S() || vd.Is4S()) { in Movi()
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 2924 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
2943 (vm.Is2S() && vd.Is2D()) || (vm.Is16B() && vd.Is8H()) ||
2955 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
2993 V(sqdmlal, NEON_SQDMLAL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2995 V(sqdmlsl, NEON_SQDMLSL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
2997 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
3275 VIXL_ASSERT(vd.Is2S() || vd.Is4S());
3580 VIXL_ASSERT((vd.Is4S() && vn.Is4H()) || (vd.Is2D() && vn.Is2S()));
3598 VIXL_ASSERT((vn.Is4S() && vd.Is4H()) || (vn.Is2D() && vd.Is2S()));
3621 VIXL_ASSERT(vd.Is2S()
[all...] |
| H A D | macro-assembler-aarch64.cc | 1177 } else if (vd.Is2S() || vd.Is4S()) { in Emit()
1649 if (vd.Is1S() || vd.Is2S() || vd.Is4S()) { in Emit()
1694 VIXL_ASSERT(vd.Is1S() || vd.Is2S() || vd.Is4S()); in Emit()
1717 if (vd.Is1S() || vd.Is2S() || vd.Is4S()) { in Emit()
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| H A D | registers-aarch64.h | 368 bool Is2S() const { return IsD() && IsLaneSizeS(); }
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