Searched refs:Is1D (Results 1 - 8 of 8) sorted by relevance
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1436 DCHECK((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) || in NEON3DifferentL()
1537 DCHECK(!vd.Is1D()); in NEONPerm()
1623 (vd.Is1S() && vn.Is1D())); in NEONShiftImmediateN()
1637 DCHECK(vd.IsVector() || vd.Is1D()); in shl()
1642 DCHECK(vd.IsVector() || vd.Is1D()); in sli()
1695 DCHECK(vd.IsVector() || vd.Is1D()); in sri()
1700 DCHECK(vd.IsVector() || vd.Is1D()); in sshr()
1705 DCHECK(vd.IsVector() || vd.Is1D()); in ushr()
1710 DCHECK(vd.IsVector() || vd.Is1D()); in srshr()
1715 DCHECK(vd.IsVector() || vd.Is1D()); in urshr()
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| H A D | register-arm64.h | 162 // So, for example, Is8B() implies IsD(), and Is1D() implies IsD, but IsD()
163 // does not imply Is1D() or Is8B().
165 // as Is8B(), Is1D(), etc. in the VRegister class.
377 bool Is1D() const { return (Is64Bits() && (lane_count_ == 1)); } in Is1D() function in v8::internal::VRegister
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| H A D | macro-assembler-arm64-inl.h | 670 DCHECK(vd.Is1D() || vd.Is2D()); in Fmov()
692 if (vd.Is1D() || vd.Is2D()) { in Fmov()
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| H A D | macro-assembler-arm64.cc | 538 if (vd.Is1D()) { in Movi64bitHelper()
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 2575 VIXL_ASSERT(vt.IsVector() || vt.Is1D()); in LoadStoreStruct()
2922 VIXL_ASSERT((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) ||
3255 VIXL_ASSERT(vd.Is1D());
3303 VIXL_ASSERT(vn.Is1H() || vn.Is1S() || vn.Is1D());
3323 (vd.Is1D() && CPUHas(CPUFeatures::kNEON)));
3324 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
3347 VIXL_ASSERT(vd.Is1H() || vd.Is1S() || vd.Is1D());
3355 VIXL_ASSERT((index == 1) && vd.Is1D() && rn.IsX());
3363 VIXL_ASSERT((index == 1) && vn.Is1D() && rd.IsX());
3381 VIXL_ASSERT(vd.Is1D());
[all...] |
| H A D | registers-aarch64.h | 212 bool IsFPRegister() const { return Is1H() || Is1S() || Is1D(); }
343 // So, for example, Is8B() implies IsD(), and Is1D() implies IsD, but IsD()
344 // does not imply Is1D() or Is8B().
346 // as Is8B(), Is1D(), etc.
354 // example, reg.Is1D() implies DRegister(reg).IsValid(), but reg.IsD() does
359 bool Is1D() const { return IsD() && IsScalar(); }
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| H A D | macro-assembler-aarch64.cc | 1153 if (vd.Is1D()) { in Emit()
1654 VIXL_ASSERT(vd.Is1D() || vd.Is2D()); in Emit()
1689 if (vd.Is1D() || vd.Is2D()) { in Emit()
1722 if (vd.Is1D() || vd.Is2D()) { in Emit()
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| H A D | macro-assembler-aarch64.h | 1663 if (vd.Is1D() && (index == 0)) { in Fmov()
1672 if (vn.Is1D() && (index == 0)) { in Fmov()
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