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/third_party/json/tests/thirdparty/Fuzzer/
H A DFuzzerCorpus.h46 for (auto II : Inputs) in ~InputCorpus()
49 size_t size() const { return Inputs.size(); } in size()
52 for (auto II : Inputs) in SizeInBytes()
58 for (auto II : Inputs) in NumActiveUnits()
62 bool empty() const { return Inputs.empty(); } in empty()
63 const Unit &operator[] (size_t Idx) const { return Inputs[Idx]->U; } in operator []()
68 Printf("ADD_TO_CORPUS %zd NF %zd\n", Inputs.size(), NumFeatures); in AddToCorpus()
71 Inputs.push_back(new InputInfo()); in AddToCorpus()
72 InputInfo &II = *Inputs.back(); in AddToCorpus()
84 InputInfo &II = *Inputs[ChooseUnitIdxToMutat in ChooseUnitToMutate()
206 std::vector<InputInfo*> Inputs; global() variable
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp301 // (1) Given an instruction MI, and the map with input values "Inputs",
314 virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
318 virtual bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
321 virtual bool rewrite(MachineInstr &MI, const CellMap &Inputs) = 0;
359 bool getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC);
366 const CellMap &Inputs, bool &Result);
368 const CellMap &Inputs, bool &Result);
370 const CellMap &Inputs, bool &Result);
378 bool evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs,
383 const CellMap &Inputs, LatticeCel
1081 getCell(const RegisterSubReg &R, const CellMap &Inputs, LatticeCell &RC) getCell() argument
1107 evaluateCMPrr(uint32_t Cmp, const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, bool &Result) evaluateCMPrr() argument
1146 evaluateCMPri(uint32_t Cmp, const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, bool &Result) evaluateCMPri() argument
1173 evaluateCMPrp(uint32_t Cmp, const RegisterSubReg &R1, uint64_t Props2, const CellMap &Inputs, bool &Result) evaluateCMPrp() argument
1366 evaluateCOPY(const RegisterSubReg &R1, const CellMap &Inputs, LatticeCell &Result) evaluateCOPY() argument
1371 evaluateANDrr(const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) evaluateANDrr() argument
1402 evaluateANDri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result) evaluateANDri() argument
1438 evaluateORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) evaluateORrr() argument
1469 evaluateORri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result) evaluateORri() argument
1505 evaluateXORrr(const RegisterSubReg &R1, const RegisterSubReg &R2, const CellMap &Inputs, LatticeCell &Result) evaluateXORrr() argument
1534 evaluateXORri(const RegisterSubReg &R1, const APInt &A2, const CellMap &Inputs, LatticeCell &Result) evaluateXORri() argument
1567 evaluateZEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, const CellMap &Inputs, LatticeCell &Result) evaluateZEXTr() argument
1598 evaluateSEXTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, const CellMap &Inputs, LatticeCell &Result) evaluateSEXTr() argument
1663 evaluateCLBr(const RegisterSubReg &R1, bool Zeros, bool Ones, const CellMap &Inputs, LatticeCell &Result) evaluateCLBr() argument
1698 evaluateCTBr(const RegisterSubReg &R1, bool Zeros, bool Ones, const CellMap &Inputs, LatticeCell &Result) evaluateCTBr() argument
1733 evaluateEXTRACTr(const RegisterSubReg &R1, unsigned Width, unsigned Bits, unsigned Offset, bool Signed, const CellMap &Inputs, LatticeCell &Result) evaluateEXTRACTr() argument
1791 evaluateSplatr(const RegisterSubReg &R1, unsigned Bits, unsigned Count, const CellMap &Inputs, LatticeCell &Result) evaluateSplatr() argument
1926 evaluate(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) evaluate() argument
2260 evaluate(const MachineInstr &BrI, const CellMap &Inputs, SetVector<const MachineBasicBlock*> &Targets, bool &FallsThru) evaluate() argument
2329 rewrite(MachineInstr &MI, const CellMap &Inputs) rewrite() argument
2517 evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, const CellMap &Inputs, LatticeCell &Result) evaluateHexRSEQ32() argument
2554 evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) evaluateHexCompare() argument
2599 evaluateHexCompare2(unsigned Opc, const MachineOperand &Src1, const MachineOperand &Src2, const CellMap &Inputs, bool &Result) evaluateHexCompare2() argument
2629 evaluateHexLogical(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) evaluateHexLogical() argument
2676 evaluateHexCondMove(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) evaluateHexCondMove() argument
2719 evaluateHexExt(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) evaluateHexExt() argument
2763 evaluateHexVector1(const MachineInstr &MI, const CellMap &Inputs, CellMap &Outputs) evaluateHexVector1() argument
2792 rewriteHexConstDefs(MachineInstr &MI, const CellMap &Inputs, bool &AllDefs) rewriteHexConstDefs() argument
2956 rewriteHexConstUses(MachineInstr &MI, const CellMap &Inputs) rewriteHexConstUses() argument
3133 rewriteHexBranch(MachineInstr &BrI, const CellMap &Inputs) rewriteHexBranch() argument
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/third_party/vixl/test/aarch32/traces/
H A Dsimulator-cond-rd-memop-immediate-512-ldrh-a32.h37 const Inputs kOutputs_Ldrh_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Ldrh_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Ldrh_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Ldrh_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Ldrh_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Ldrh_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Ldrh_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Ldrh_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Ldrh_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Ldrh_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-immediate-512-ldrsb-a32.h37 const Inputs kOutputs_Ldrsb_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Ldrsb_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Ldrsb_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Ldrsb_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Ldrsb_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Ldrsb_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Ldrsb_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Ldrsb_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Ldrsb_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Ldrsb_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-immediate-512-ldrsh-a32.h37 const Inputs kOutputs_Ldrsh_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Ldrsh_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Ldrsh_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Ldrsh_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Ldrsh_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Ldrsh_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Ldrsh_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Ldrsh_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Ldrsh_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Ldrsh_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-immediate-512-strh-a32.h37 const Inputs kOutputs_Strh_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Strh_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Strh_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Strh_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Strh_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Strh_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Strh_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Strh_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Strh_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Strh_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-immediate-8192-ldr-a32.h37 const Inputs kOutputs_Ldr_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Ldr_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Ldr_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Ldr_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Ldr_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Ldr_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Ldr_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Ldr_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Ldr_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Ldr_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-immediate-8192-ldrb-a32.h37 const Inputs kOutputs_Ldrb_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Ldrb_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Ldrb_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Ldrb_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Ldrb_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Ldrb_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Ldrb_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Ldrb_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Ldrb_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Ldrb_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-immediate-8192-str-a32.h37 const Inputs kOutputs_Str_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Str_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Str_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Str_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Str_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Str_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Str_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Str_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Str_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Str_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-immediate-8192-strb-a32.h37 const Inputs kOutputs_Strb_Condition_eq_r0_r1_plus_0_Offset[] = {
54 const Inputs kOutputs_Strb_Condition_ne_r0_r1_plus_0_Offset[] = {
71 const Inputs kOutputs_Strb_Condition_cs_r0_r1_plus_0_Offset[] = {
88 const Inputs kOutputs_Strb_Condition_cc_r0_r1_plus_0_Offset[] = {
105 const Inputs kOutputs_Strb_Condition_mi_r0_r1_plus_0_Offset[] = {
122 const Inputs kOutputs_Strb_Condition_pl_r0_r1_plus_0_Offset[] = {
139 const Inputs kOutputs_Strb_Condition_vs_r0_r1_plus_0_Offset[] = {
156 const Inputs kOutputs_Strb_Condition_vc_r0_r1_plus_0_Offset[] = {
173 const Inputs kOutputs_Strb_Condition_hi_r0_r1_plus_0_Offset[] = {
190 const Inputs kOutputs_Strb_Condition_ls_r0_r1_plus_0_Offse
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H A Dsimulator-cond-rd-memop-rs-shift-amount-1to32-strb-a32.h37 const Inputs kOutputs_Strb_Condition_eq_r0_r1_plus_r8_LSR_1_Offset[] = {
54 const Inputs kOutputs_Strb_Condition_ne_r0_r1_plus_r8_LSR_1_Offset[] = {
71 const Inputs kOutputs_Strb_Condition_cs_r0_r1_plus_r8_LSR_1_Offset[] = {
88 const Inputs kOutputs_Strb_Condition_cc_r0_r1_plus_r8_LSR_1_Offset[] = {
105 const Inputs kOutputs_Strb_Condition_mi_r0_r1_plus_r8_LSR_1_Offset[] = {
122 const Inputs kOutputs_Strb_Condition_pl_r0_r1_plus_r8_LSR_1_Offset[] = {
139 const Inputs kOutputs_Strb_Condition_vs_r0_r1_plus_r8_LSR_1_Offset[] = {
156 const Inputs kOutputs_Strb_Condition_vc_r0_r1_plus_r8_LSR_1_Offset[] = {
173 const Inputs kOutputs_Strb_Condition_hi_r0_r1_plus_r8_LSR_1_Offset[] = {
190 const Inputs kOutputs_Strb_Condition_ls_r0_r1_plus_r8_LSR_1_Offse
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H A Dsimulator-cond-rd-memop-rs-str-a32.h37 const Inputs kOutputs_Str_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Str_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Str_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Str_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Str_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Str_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Str_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Str_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Str_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Str_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-strb-a32.h37 const Inputs kOutputs_Strb_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Strb_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Strb_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Strb_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Strb_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Strb_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Strb_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Strb_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Strb_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Strb_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-strh-a32.h37 const Inputs kOutputs_Strh_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Strh_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Strh_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Strh_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Strh_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Strh_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Strh_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Strh_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Strh_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Strh_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-ldr-a32.h37 const Inputs kOutputs_Ldr_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Ldr_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Ldr_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Ldr_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Ldr_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Ldr_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Ldr_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Ldr_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Ldr_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Ldr_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-ldrb-a32.h37 const Inputs kOutputs_Ldrb_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Ldrb_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Ldrb_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Ldrb_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Ldrb_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Ldrb_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Ldrb_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Ldrb_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Ldrb_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Ldrb_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-ldrh-a32.h37 const Inputs kOutputs_Ldrh_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Ldrh_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Ldrh_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Ldrh_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Ldrh_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Ldrh_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Ldrh_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Ldrh_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Ldrh_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Ldrh_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-ldrsb-a32.h37 const Inputs kOutputs_Ldrsb_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Ldrsb_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Ldrsb_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Ldrsb_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Ldrsb_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Ldrsb_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Ldrsb_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Ldrsb_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Ldrsb_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Ldrsb_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-ldrsh-a32.h37 const Inputs kOutputs_Ldrsh_Condition_eq_r0_r1_plus_r8_Offset[] = {
54 const Inputs kOutputs_Ldrsh_Condition_ne_r0_r1_plus_r8_Offset[] = {
71 const Inputs kOutputs_Ldrsh_Condition_cs_r0_r1_plus_r8_Offset[] = {
88 const Inputs kOutputs_Ldrsh_Condition_cc_r0_r1_plus_r8_Offset[] = {
105 const Inputs kOutputs_Ldrsh_Condition_mi_r0_r1_plus_r8_Offset[] = {
122 const Inputs kOutputs_Ldrsh_Condition_pl_r0_r1_plus_r8_Offset[] = {
139 const Inputs kOutputs_Ldrsh_Condition_vs_r0_r1_plus_r8_Offset[] = {
156 const Inputs kOutputs_Ldrsh_Condition_vc_r0_r1_plus_r8_Offset[] = {
173 const Inputs kOutputs_Ldrsh_Condition_hi_r0_r1_plus_r8_Offset[] = {
190 const Inputs kOutputs_Ldrsh_Condition_ls_r0_r1_plus_r8_Offse
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H A Dsimulator-cond-rd-memop-rs-shift-amount-1to31-ldr-a32.h37 const Inputs kOutputs_Ldr_Condition_eq_r0_r1_plus_r8_LSL_1_Offset[] = {
54 const Inputs kOutputs_Ldr_Condition_ne_r0_r1_plus_r8_LSL_1_Offset[] = {
71 const Inputs kOutputs_Ldr_Condition_cs_r0_r1_plus_r8_LSL_1_Offset[] = {
88 const Inputs kOutputs_Ldr_Condition_cc_r0_r1_plus_r8_LSL_1_Offset[] = {
105 const Inputs kOutputs_Ldr_Condition_mi_r0_r1_plus_r8_LSL_1_Offset[] = {
122 const Inputs kOutputs_Ldr_Condition_pl_r0_r1_plus_r8_LSL_1_Offset[] = {
139 const Inputs kOutputs_Ldr_Condition_vs_r0_r1_plus_r8_LSL_1_Offset[] = {
156 const Inputs kOutputs_Ldr_Condition_vc_r0_r1_plus_r8_LSL_1_Offset[] = {
173 const Inputs kOutputs_Ldr_Condition_hi_r0_r1_plus_r8_LSL_1_Offset[] = {
190 const Inputs kOutputs_Ldr_Condition_ls_r0_r1_plus_r8_LSL_1_Offse
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H A Dsimulator-cond-rd-memop-rs-shift-amount-1to31-ldrb-a32.h37 const Inputs kOutputs_Ldrb_Condition_eq_r0_r1_plus_r8_LSL_1_Offset[] = {
54 const Inputs kOutputs_Ldrb_Condition_ne_r0_r1_plus_r8_LSL_1_Offset[] = {
71 const Inputs kOutputs_Ldrb_Condition_cs_r0_r1_plus_r8_LSL_1_Offset[] = {
88 const Inputs kOutputs_Ldrb_Condition_cc_r0_r1_plus_r8_LSL_1_Offset[] = {
105 const Inputs kOutputs_Ldrb_Condition_mi_r0_r1_plus_r8_LSL_1_Offset[] = {
122 const Inputs kOutputs_Ldrb_Condition_pl_r0_r1_plus_r8_LSL_1_Offset[] = {
139 const Inputs kOutputs_Ldrb_Condition_vs_r0_r1_plus_r8_LSL_1_Offset[] = {
156 const Inputs kOutputs_Ldrb_Condition_vc_r0_r1_plus_r8_LSL_1_Offset[] = {
173 const Inputs kOutputs_Ldrb_Condition_hi_r0_r1_plus_r8_LSL_1_Offset[] = {
190 const Inputs kOutputs_Ldrb_Condition_ls_r0_r1_plus_r8_LSL_1_Offse
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H A Dsimulator-cond-rd-memop-rs-shift-amount-1to31-str-a32.h37 const Inputs kOutputs_Str_Condition_eq_r0_r1_plus_r8_LSL_1_Offset[] = {
54 const Inputs kOutputs_Str_Condition_ne_r0_r1_plus_r8_LSL_1_Offset[] = {
71 const Inputs kOutputs_Str_Condition_cs_r0_r1_plus_r8_LSL_1_Offset[] = {
88 const Inputs kOutputs_Str_Condition_cc_r0_r1_plus_r8_LSL_1_Offset[] = {
105 const Inputs kOutputs_Str_Condition_mi_r0_r1_plus_r8_LSL_1_Offset[] = {
122 const Inputs kOutputs_Str_Condition_pl_r0_r1_plus_r8_LSL_1_Offset[] = {
139 const Inputs kOutputs_Str_Condition_vs_r0_r1_plus_r8_LSL_1_Offset[] = {
156 const Inputs kOutputs_Str_Condition_vc_r0_r1_plus_r8_LSL_1_Offset[] = {
173 const Inputs kOutputs_Str_Condition_hi_r0_r1_plus_r8_LSL_1_Offset[] = {
190 const Inputs kOutputs_Str_Condition_ls_r0_r1_plus_r8_LSL_1_Offse
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H A Dsimulator-cond-rd-memop-rs-shift-amount-1to31-strb-a32.h37 const Inputs kOutputs_Strb_Condition_eq_r0_r1_plus_r8_LSL_1_Offset[] = {
54 const Inputs kOutputs_Strb_Condition_ne_r0_r1_plus_r8_LSL_1_Offset[] = {
71 const Inputs kOutputs_Strb_Condition_cs_r0_r1_plus_r8_LSL_1_Offset[] = {
88 const Inputs kOutputs_Strb_Condition_cc_r0_r1_plus_r8_LSL_1_Offset[] = {
105 const Inputs kOutputs_Strb_Condition_mi_r0_r1_plus_r8_LSL_1_Offset[] = {
122 const Inputs kOutputs_Strb_Condition_pl_r0_r1_plus_r8_LSL_1_Offset[] = {
139 const Inputs kOutputs_Strb_Condition_vs_r0_r1_plus_r8_LSL_1_Offset[] = {
156 const Inputs kOutputs_Strb_Condition_vc_r0_r1_plus_r8_LSL_1_Offset[] = {
173 const Inputs kOutputs_Strb_Condition_hi_r0_r1_plus_r8_LSL_1_Offset[] = {
190 const Inputs kOutputs_Strb_Condition_ls_r0_r1_plus_r8_LSL_1_Offse
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H A Dsimulator-cond-rd-memop-rs-shift-amount-1to32-ldr-a32.h37 const Inputs kOutputs_Ldr_Condition_eq_r0_r1_plus_r8_LSR_1_Offset[] = {
54 const Inputs kOutputs_Ldr_Condition_ne_r0_r1_plus_r8_LSR_1_Offset[] = {
71 const Inputs kOutputs_Ldr_Condition_cs_r0_r1_plus_r8_LSR_1_Offset[] = {
88 const Inputs kOutputs_Ldr_Condition_cc_r0_r1_plus_r8_LSR_1_Offset[] = {
105 const Inputs kOutputs_Ldr_Condition_mi_r0_r1_plus_r8_LSR_1_Offset[] = {
122 const Inputs kOutputs_Ldr_Condition_pl_r0_r1_plus_r8_LSR_1_Offset[] = {
139 const Inputs kOutputs_Ldr_Condition_vs_r0_r1_plus_r8_LSR_1_Offset[] = {
156 const Inputs kOutputs_Ldr_Condition_vc_r0_r1_plus_r8_LSR_1_Offset[] = {
173 const Inputs kOutputs_Ldr_Condition_hi_r0_r1_plus_r8_LSR_1_Offset[] = {
190 const Inputs kOutputs_Ldr_Condition_ls_r0_r1_plus_r8_LSR_1_Offse
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_instr_tex.h79 struct Inputs { struct in r600::TexInstr
80 Inputs(const nir_tex_instr& instr, ValueFactory &vf);
158 static auto prepare_source(nir_tex_instr *tex, const Inputs& inputs, Shader &shader) -> RegisterVec4;
160 static bool emit_buf_txf(nir_tex_instr *tex, Inputs& src, Shader& shader);
161 static bool emit_tex_txf(nir_tex_instr *tex, Inputs& src, Shader& shader);
162 static bool emit_tex_tex_ms_direct(nir_tex_instr *tex, Inputs& src, Shader& shader);
163 static bool emit_tex_tex_ms(nir_tex_instr *tex, Inputs& src, Shader& shader);
164 static bool emit_tex_tex(nir_tex_instr *tex, Inputs& src, Shader& shader);
165 static bool emit_tex_txl_txb(nir_tex_instr *tex, Inputs& src, Shader& shader);
166 static bool emit_tex_txs(nir_tex_instr *tex, Inputs
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