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Searched refs:GetReg (Results 1 - 4 of 4) sorted by relevance

/third_party/vixl/src/aarch32/
H A Dinstructions-aarch32.h123 uint32_t GetReg() const { return value_; }
133 bool Is(CPURegister ref) const { return GetReg() == ref.GetReg(); }
782 uint32_t GetReg() const { return reg_; }
890 uint32_t GetReg() const { return reg_; }
931 uint32_t GetReg() const { return reg_; }
H A Ddisasm-aarch32.h178 DRegister GetReg() const { return reg_; } in GetReg() function in vixl::aarch32::Disassembler::IndexedRegisterPrinter
182 return os << reg.GetReg() << "[" << reg.GetIndex() << "]"; in operator <<()
H A Dassembler-aarch32.cc7399 EmitT32_32(0xf3ef8000U | (rd.GetCode() << 8) | (spec_reg.GetReg() << 20)); in mrs()
7407 (spec_reg.GetReg() << 22)); in mrs()
7426 ((spec_reg.GetReg() & 0xf) << 16) | in msr()
7427 ((spec_reg.GetReg() & 0x10) << 18) | in msr()
7438 EmitT32_32(0xf3808000U | ((spec_reg.GetReg() & 0xf) << 8) | in msr()
7439 ((spec_reg.GetReg() & 0x10) << 16) | (rn.GetCode() << 16)); in msr()
7447 ((spec_reg.GetReg() & 0xf) << 16) | in msr()
7448 ((spec_reg.GetReg() & 0x10) << 18) | rn.GetCode()); in msr()
21259 EmitT32_32(0xeef00a10U | (rt.GetCode() << 12) | (spec_reg.GetReg() << 16)); in vmrs()
21266 (spec_reg.GetReg() << 1 in vmrs()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp1205 Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1208 .addDef(GetReg)
1210 MRI.setType(GetReg, S32);
1215 .addUse(GetReg)

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