| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-fp-aarch64.cc | 3454 __ Fcvt(d0, s16);
3455 __ Fcvt(d1, s17);
3456 __ Fcvt(d2, s18);
3457 __ Fcvt(d3, s19);
3458 __ Fcvt(d4, s20);
3459 __ Fcvt(d5, s21);
3460 __ Fcvt(d6, s22);
3461 __ Fcvt(d7, s23);
3462 __ Fcvt(d8, s24);
3463 __ Fcvt(d
[all...] |
| H A D | test-disasm-sve-aarch64.cc | 1939 COMPARE_MACRO(Fcvt(z5.VnH(), p2.Zeroing(), z11.VnD()), in TEST()
1942 COMPARE_MACRO(Fcvt(z30.VnS(), p7.Zeroing(), z0.VnD()), in TEST()
1945 COMPARE_MACRO(Fcvt(z10.VnD(), p0.Zeroing(), z17.VnH()), in TEST()
1948 COMPARE_MACRO(Fcvt(z28.VnS(), p3.Zeroing(), z27.VnH()), in TEST()
1951 COMPARE_MACRO(Fcvt(z9.VnD(), p7.Zeroing(), z0.VnS()), in TEST()
1954 COMPARE_MACRO(Fcvt(z27.VnH(), p7.Zeroing(), z9.VnS()), in TEST()
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| H A D | test-simulator-aarch64.cc | 5101 __ Fcvt(input_1.D(), input_1); in GenerateSum()
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| H A D | test-assembler-sve-aarch64.cc | 318 __ Fcvt(h1, d30);
15451 // Fcvt variants have no zeroing predication form.
18149 &MacroAssembler::Fcvt, // Merging form.
18150 &MacroAssembler::Fcvt); // Zerging form.
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| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 369 __ Fcvt(PickV(other_size), PickV(size)); in GenerateFPSequence()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.cc | 3524 Fcvt(temp0.VReg(), args[i].VReg()); in TruncateDoubleToI()
3541 Fcvt(pcs[i].VReg(), args[i].VReg()); in TruncateDoubleToI()
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| H A D | macro-assembler-arm64-inl.h | 558 void TurboAssembler::Fcvt(const VRegister& fd, const VRegister& fn) { in Fcvt() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64.h | 1156 inline void Fcvt(const VRegister& fd, const VRegister& fn);
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1503 Fcvt(dst.fp().S(), src.fp().D()); in emit_type_conversion()
1521 Fcvt(dst.fp().D(), src.fp().S()); in emit_type_conversion()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1711 __ Fcvt(i.OutputDoubleRegister(), i.InputDoubleRegister(0).S()); in AssembleArchInstruction()
1714 __ Fcvt(i.OutputDoubleRegister().S(), i.InputDoubleRegister(0)); in AssembleArchInstruction()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 1522 void Fcvt(const VRegister& vd, const VRegister& vn) { in Fcvt() function in vixl::aarch64::MacroAssembler
4519 void Fcvt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) { in Fcvt() function in vixl::aarch64::MacroAssembler
4524 void Fcvt(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) { in Fcvt() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.cc | 2738 Fcvt(VRegister(pcs[i]), VRegister(args[i])); in Emit()
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