Searched refs:FPR (Results 1 - 4 of 4) sorted by relevance
| /third_party/elfutils/backends/ |
| H A D | s390_corenote.c | 66 #define FPR(at, n, dwreg) \ macro
71 FPR (1 + 0, 1, 16), /* f0 */
72 FPR (1 + 1, 1, 20), /* f1 */
73 FPR (1 + 2, 1, 17), /* f2 */
74 FPR (1 + 3, 1, 21), /* f3 */
75 FPR (1 + 4, 1, 18), /* f4 */
76 FPR (1 + 5, 1, 22), /* f5 */
77 FPR (1 + 6, 1, 19), /* f6 */
78 FPR (1 + 7, 1, 23), /* f7 */
79 FPR (
88 #undef FPR global() macro
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 71 // The FPR register bank is fully defined by all the registers in in AArch64RegisterBankInfo()
124 CHECK_VALUEMAP(FPR, 16); in AArch64RegisterBankInfo()
125 CHECK_VALUEMAP(FPR, 32); in AArch64RegisterBankInfo()
126 CHECK_VALUEMAP(FPR, 64); in AArch64RegisterBankInfo()
127 CHECK_VALUEMAP(FPR, 128); in AArch64RegisterBankInfo()
128 CHECK_VALUEMAP(FPR, 256); in AArch64RegisterBankInfo()
129 CHECK_VALUEMAP(FPR, 512); in AArch64RegisterBankInfo()
142 CHECK_VALUEMAP_3OPS(FPR, 32); in AArch64RegisterBankInfo()
143 CHECK_VALUEMAP_3OPS(FPR, 64); in AArch64RegisterBankInfo()
144 CHECK_VALUEMAP_3OPS(FPR, 12 in AArch64RegisterBankInfo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZMachineFunctionInfo.h | 73 void setVarArgsFirstFPR(unsigned FPR) { VarArgsFirstFPR = FPR; } in setVarArgsFirstFPR() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 3314 /// FPR - The set of FP registers that should be allocated for arguments
3316 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, local
3417 // However, if the argument is actually passed in an FPR or a VR, in CalculateStackSlotUsed()
3991 VReg = MF.addLiveIn(FPR[FPR_idx], in LowerFormalArguments_64SVR4()
3996 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
4398 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); in LowerFormalArguments_Darwin()
4400 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); in LowerFormalArguments_Darwin()
6222 // routines always in both locations (FPR *and* GPR or stack slot). in LowerCall_64SVR4()
6226 // First load the argument into the next available FPR. in LowerCall_64SVR4()
6228 RegsToPass.push_back(std::make_pair(FPR[FPR_id in LowerCall_64SVR4()
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