Searched refs:FPCR (Results 1 - 12 of 12) sorted by relevance
| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 116 case FPCR: in DefaultValueFor()
378 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in ResetState()
1369 PrintSystemRegister(FPCR);
1597 case FPCR: {
3178 break; // Use FPCR rounding mode.
3360 case FPCR:
3374 case FPCR:
3376 LogSystemRegister(FPCR);
4054 break; // Use FPCR rounding mode.
|
| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-fp-aarch64.cc | 2909 // VIXL only supports the round-to-nearest FPCR mode, so this test has the
3263 // VIXL only supports the round-to-nearest FPCR mode, and it doesn't support
5292 // Enable Default-NaN mode in the FPCR.
5293 __ Mrs(x0, FPCR);
5295 __ Msr(FPCR, x1);
5333 // Restore FPCR.
5334 __ Msr(FPCR, x0);
5420 // Enable Default-NaN mode in the FPCR.
5421 __ Mrs(x0, FPCR);
5423 __ Msr(FPCR, x
[all...] |
| H A D | test-assembler-aarch64.cc | 6988 // Read the default FPCR.
6989 __ Mrs(x6, FPCR);
7000 // FPCR
7001 // The default FPCR on Linux-based platforms is 0.
7135 // All FPCR fields that must be implemented: AHP, DN, FZ, RMode
7168 __ Mrs(old_fpcr, FPCR);
7170 // All core FPCR fields must be writable.
7172 __ Msr(FPCR, x8);
7173 __ Mrs(x8, FPCR);
7176 // All FPCR field
[all...] |
| H A D | test-disasm-aarch64.cc | 2611 COMPARE(mrs(x15, FPCR), "mrs x15, fpcr"); in TEST()
2628 COMPARE(msr(FPCR, x15), "msr fpcr, x15"); in TEST()
|
| H A D | test-cpu-features-aarch64.cc | 379 TEST_NONE(mrs_0, mrs(x0, FPCR))
380 TEST_NONE(msr_0, msr(FPCR, x0))
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 279 /* FPCR */ \
284 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
441 FPCR = ((0x1 << SysO0_offset) | (0x3 << SysOp1_offset) | (0x4 << CRn_offset) | enumerator
|
| H A D | macro-assembler-arm64.cc | 1444 Mrs(fpcr, FPCR); in AssertFPCRState()
|
| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| H A D | disasm-arm64.cc | 1463 case FPCR: in VisitSystem()
1478 case FPCR: in VisitSystem()
|
| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 63 case FPCR: in DefaultValueFor()
575 fpcr_ = SimSystemRegister::DefaultValueFor(FPCR); in Simulator()
1330 PrintSystemRegister(FPCR); in Simulator()
1726 case FPCR: { in Simulator()
6411 break; // Use FPCR rounding mode. in Simulator()
6416 break; // Use FPCR rounding mode. in Simulator()
6432 break; // Use FPCR rounding mode. in Simulator()
6746 case FPCR: in Simulator()
6748 LogSystemRegister(FPCR); in Simulator()
6759 case FPCR in Simulator()
[all...] |
| H A D | constants-aarch64.h | 234 /* FPCR */ \
239 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
501 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, enumerator
|
| H A D | disasm-aarch64.cc | 6900 case FPCR: in Disassembler()
|
| H A D | assembler-aarch64.cc | 6869 case FPCR:
|
Completed in 107 milliseconds