| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 426 setOperationAction(ISD::FNEG, VT, Expand); in AMDGPUTargetLowering()
499 setTargetDAGCombine(ISD::FNEG); in AMDGPUTargetLowering()
1585 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2477 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R); in LowerINT_TO_FP32()
3523 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
3529 if (RHS.getOpcode() == ISD::FABS || RHS.getOpcode() == ISD::FNEG) { in foldFreeOpFromSelect()
3536 if ((LHS.getOpcode() == ISD::FNEG || LHS.getOpcode() == ISD::FABS) && CRHS) { in foldFreeOpFromSelect()
3548 if (LHS.getOpcode() == ISD::FNEG && fnegFoldsIntoOp(Opc)) in foldFreeOpFromSelect()
3555 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
[all...] |
| H A D | AMDGPUISelDAGToDAG.cpp | 2401 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3ModsImpl()
2441 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
2474 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2485 if (Lo.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
2490 if (Hi.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
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| H A D | SIISelLowering.cpp | 596 setOperationAction(ISD::FNEG, MVT::v2f16, Legal); in SITargetLowering()
668 setOperationAction(ISD::FNEG, MVT::v4f16, Custom); in SITargetLowering()
681 setOperationAction(ISD::FNEG, MVT::v2f16, Custom); in SITargetLowering()
4081 case ISD::FNEG: in LowerOperation()
4364 case ISD::FNEG: { in ReplaceNodeResults()
7579 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
7723 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32()
7821 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0); in LowerFDIV64()
8796 case ISD::FNEG: in isCanonicalized()
9286 if ((Vec.getOpcode() == ISD::FNEG || in performExtractVectorEltCombine()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1585 case ISD::FNEG: return visitFNEG(N); in visit()
11109 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
11132 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp); in foldBitcastedFPLogic()
11222 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
11235 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
11254 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
11779 DAG.getNode(ISD::FNEG, SL, VT, N1), Flags); in visitFSUBForFMACombine()
11786 DAG.getNode(ISD::FNEG, SL, VT, in visitFSUBForFMACombine()
11792 if (N0.getOpcode() == ISD::FNEG && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
11797 DAG.getNode(ISD::FNEG, S in visitFSUBForFMACombine()
[all...] |
| H A D | LegalizeFloatTypes.cpp | 100 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
458 // Expand Y = FNEG(X) -> Y = X ^ sign mask in SoftenFloatRes_FNEG()
1162 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1248 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1413 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1414 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
2117 case ISD::FNEG: in PromoteFloatResult()
|
| H A D | LegalizeVectorOps.cpp | 410 case ISD::FNEG: in LegalizeOp()
875 case ISD::FNEG: in Expand()
1412 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB. in ExpandFNEG()
1421 // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal, in ExpandFSUB()
1425 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
|
| H A D | SelectionDAGBuilder.h | 690 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } in visitFNeg()
|
| H A D | SelectionDAGDumper.cpp | 192 case ISD::FNEG: return "fneg"; in getOperationName()
|
| H A D | LegalizeDAG.cpp | 1524 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1526 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
3156 case ISD::FNEG:
3157 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3159 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3255 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3257 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
4507 case ISD::FNEG:
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| H A D | SelectionDAG.cpp | 4122 case ISD::FNEG:
4457 case ISD::FNEG:
4527 case ISD::FNEG:
4747 case ISD::FNEG:
4752 if (OpOpcode == ISD::FNEG) // --X -> X
4756 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
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| H A D | TargetLowering.cpp | 3775 if (N0.getOpcode() == ISD::FNEG) { in SimplifySetCC()
3779 SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1); in SimplifySetCC()
5486 if (Op.getOpcode() == ISD::FNEG) in isNegatibleForFree()
5603 if (Op.getOpcode() == ISD::FNEG)
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| H A D | LegalizeVectorTypes.cpp | 90 case ISD::FNEG: in ScalarizeVectorResult()
883 case ISD::FNEG: in SplitVectorResult()
2844 case ISD::FNEG: in WidenVectorResult()
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| H A D | FastISel.cpp | 1716 // If the target has ISD::FNEG, use it. in selectFNeg()
1718 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG, in selectFNeg()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1612 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1719 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1722 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1741 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3049 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 965 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
974 if (Op0.getOpcode() == ISD::FNEG) { in PerformDAGCombine()
1013 if (!(Op0.getOpcode() == ISD::FNEG || Op0.getOpcode() == ISD::FABS) || in PerformDAGCombine()
1019 if (Op0.getOpcode() == ISD::FNEG) { in PerformDAGCombine()
|
| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_target_gv100.cpp | 117 OPINFO(FNEG , RIC , NA , NONE, NONE, NONE, NONE);
|
| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativePPC_common.c | 180 #define FNEG (HI(63) | LO(40)) macro
2105 FAIL_IF(push_inst(compiler, FNEG | FD(dst_r) | FB(src))); in sljit_emit_fop1()
|
| H A D | sljitNativeARM_64.c | 98 #define FNEG 0x1e614000 macro
1771 FAIL_IF(push_inst(compiler, (FNEG ^ inv_bits) | VD(dst_r) | VN(src))); in sljit_emit_fop1()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1594 case FNeg: return ISD::FNEG; in InstructionOpcodeToISD()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 642 setOperationAction(ISD::FNEG, VT, Expand); in PPCTargetLowering()
880 setOperationAction(ISD::FNEG, MVT::v4f32, Legal); in PPCTargetLowering()
881 setOperationAction(ISD::FNEG, MVT::v2f64, Legal); in PPCTargetLowering()
1002 setOperationAction(ISD::FNEG , MVT::v4f64, Legal); in PPCTargetLowering()
1047 setOperationAction(ISD::FNEG , MVT::v4f32, Legal); in PPCTargetLowering()
7621 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
7640 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
7657 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 543 setOperationAction(ISD::FNEG, MVT::f16, Expand); in NVPTXTargetLowering()
544 setOperationAction(ISD::FNEG, MVT::v2f16, Expand); in NVPTXTargetLowering()
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 1176 FNEG = FNEG_s,
|
| /third_party/node/deps/v8/src/diagnostics/arm64/ |
| H A D | disasm-arm64.cc | 1170 FORMAT(FNEG, "fneg"); in VisitFPDataProcessing1Source()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 265 setOperationAction(ISD::FNEG, MVT::f128, Expand); in AArch64TargetLowering()
443 setOperationAction(ISD::FNEG, MVT::f16, Promote); in AArch64TargetLowering()
468 setOperationAction(ISD::FNEG, MVT::v4f16, Expand); in AArch64TargetLowering()
492 setOperationAction(ISD::FNEG, MVT::v8f16, Expand); in AArch64TargetLowering()
715 setOperationAction(ISD::FNEG, MVT::v1f64, Expand); in AArch64TargetLowering()
5138 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec); in LowerFCOPYSIGN()
|