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Searched refs:FCC0 (Results 1 - 15 of 15) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerMIPS32.cpp443 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_eq_d()
449 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_eq_s()
455 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ole_d()
461 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ole_s()
467 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_olt_d()
473 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_olt_s()
479 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ueq_d()
485 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ueq_s()
491 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ule_d()
497 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, in c_ule_s()
[all...]
H A DIceTargetLoweringMIPS32.cpp3940 Operand *FCC0 = OperandMIPS32FCC::create(getFunc(), OperandMIPS32FCC::FCC0); in lowerFcmp() local
3961 _movf(DestR, Zero, FCC0); in lowerFcmp()
3972 _movt(DestR, Zero, FCC0); in lowerFcmp()
3983 _movt(DestR, Zero, FCC0); in lowerFcmp()
3994 _movf(DestR, Zero, FCC0); in lowerFcmp()
4005 _movf(DestR, Zero, FCC0); in lowerFcmp()
4016 _movt(DestR, Zero, FCC0); in lowerFcmp()
4027 _movt(DestR, Zero, FCC0); in lowerFcmp()
4038 _movf(DestR, Zero, FCC0); in lowerFcmp()
[all...]
H A DIceInstMIPS32.h80 using FCC = enum { FCC0 = 0, FCC1, FCC2, FCC3, FCC4, FCC5, FCC6, FCC7 };
/third_party/node/deps/v8/src/codegen/loong64/
H A Dmacro-assembler-loong64.h120 CFRegister cd = FCC0) { in CompareF32()
125 CFRegister cd = FCC0) { in CompareIsNanF32()
130 CFRegister cd = FCC0) { in CompareF64()
135 CFRegister cd = FCC0) { in CompareIsNanF64()
139 void BranchTrueShortF(Label* target, CFRegister cc = FCC0);
140 void BranchFalseShortF(Label* target, CFRegister cc = FCC0);
142 void BranchTrueF(Label* target, CFRegister cc = FCC0);
143 void BranchFalseF(Label* target, CFRegister cc = FCC0);
516 void LoadZeroIfFPUCondition(Register dest, CFRegister = FCC0);
517 void LoadZeroIfNotFPUCondition(Register dest, CFRegister = FCC0);
119 CompareF32(FPURegister cmp1, FPURegister cmp2, FPUCondition cc, CFRegister cd = FCC0) CompareF32() argument
124 CompareIsNanF32(FPURegister cmp1, FPURegister cmp2, CFRegister cd = FCC0) CompareIsNanF32() argument
129 CompareF64(FPURegister cmp1, FPURegister cmp2, FPUCondition cc, CFRegister cd = FCC0) CompareF64() argument
134 CompareIsNanF64(FPURegister cmp1, FPURegister cmp2, CFRegister cd = FCC0) CompareIsNanF64() argument
[all...]
H A Dregister-loong64.h132 enum CFRegister { FCC0, FCC1, FCC2, FCC3, FCC4, FCC5, FCC6, FCC7 }; enumerator
H A Dmacro-assembler-loong64.cc2165 bcnez(FCC0, done); in CallRecordWriteStub()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
247 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS); in printAlias()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp88 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp101 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp669 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in createCMovFP() local
672 True.getValueType(), True, FCC0, False, Cond); in createCMovFP()
2037 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in lowerBRCOND() local
2039 FCC0, Dest, CondRes); in lowerBRCOND()
H A DMipsFastISel.cpp745 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) in emitCmp()
749 .addReg(Mips::FCC0) in emitCmp()
H A DMipsInstructionSelector.cpp792 .addUse(Mips::FCC0) in select()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp1084 RegNo = Sparc::FCC0 + intVal; in matchRegisterName()
/third_party/node/deps/v8/src/compiler/backend/loong64/
H A Dcode-generator-loong64.cc2133 __ movcf2gr(result, FCC0); in AssembleArchBoolean()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp5715 (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) in checkTargetMatchPredicate()

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