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Searched refs:FADD (Results 1 - 25 of 54) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp208 { ISD::FADD, MVT::v2f64, 2 }, // addpd in getArithmeticInstrCost()
543 { ISD::FADD, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
695 { ISD::FADD, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
752 { ISD::FADD, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
753 { ISD::FADD, MVT::f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
754 { ISD::FADD, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
755 { ISD::FADD, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
837 { ISD::FADD, MV in getArithmeticInstrCost()
[all...]
H A DX86IntrinsicsInfo.h418 X86_INTRINSIC_DATA(avx512_add_pd_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
419 X86_INTRINSIC_DATA(avx512_add_ps_512, INTR_TYPE_2OP, ISD::FADD, X86ISD::FADD_RND),
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qpu.h194 A_ALU2(FADD)
H A Dvc4_qir.h674 QIR_ALU2(FADD)
H A Dvc4_qpu_emit.c258 A(FADD), in vc4_generate_code_block()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h295 FADD, FSUB, FMUL, FDIV, FREM, enumerator
H A DTargetLowering.h655 /// takes more cycles to execute than FADD.
2248 case ISD::FADD:
2528 /// Returns true if the FADD or FSUB node passed could legally be combined with
2532 assert(N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB); in isFMADLegalForFAddFSub()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp4999 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5002 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5015 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5018 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5021 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
5036 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, in getLimitedPrecisionExp2()
5039 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, in getLimitedPrecisionExp2()
5042 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, in getLimitedPrecisionExp2()
5045 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, in getLimitedPrecisionExp2()
5048 SDValue t11 = DAG.getNode(ISD::FADD, d in getLimitedPrecisionExp2()
[all...]
H A DLegalizeVectorOps.cpp377 case ISD::FADD: in LegalizeOp()
584 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32. in Promote()
1405 DAG.getNode(ISD::FADD, DL, Node->getValueType(0), fHI, fLO)); in ExpandUINT_TO_FLOAT()
1426 TLI.isOperationLegalOrCustom(ISD::FADD, VT)) in ExpandFSUB()
H A DSelectionDAGBuilder.h695 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } in visitFAdd()
H A DLegalizeFloatTypes.cpp73 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult()
1135 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi); break; in ExpandFloatResult()
1619 // TODO: Are there fast-math-flags to propagate to this FADD? in ExpandFloatRes_XINT_TO_FP()
1620 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, in ExpandFloatRes_XINT_TO_FP()
2126 case ISD::FADD: in PromoteFloatResult()
H A DDAGCombiner.cpp1570 case ISD::FADD: return visitFADD(N); in visit()
11512 /// Try to perform FMA combining on a given FADD node.
11570 // Note: Commutes FADD operands. in visitFADDForFMACombine()
11593 // Note: Commutes FADD operands. in visitFADDForFMACombine()
12071 if (X.getOpcode() == ISD::FADD && (Aggressive || X->hasOneUse())) { in visitFMULForFMADistributiveCombine()
12142 return DAG.getNode(ISD::FADD, DL, VT, N0, N1, Flags); in visitFADD()
12146 return DAG.getNode(ISD::FADD, DL, VT, N1, N0, Flags); in visitFADD()
12181 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags); in visitFADD()
12187 SDValue Add = DAG.getNode(ISD::FADD, DL, VT, B, B, Flags); in visitFADD()
12213 if (N1CFP && N0.getOpcode() == ISD::FADD in visitFADD()
[all...]
H A DSelectionDAGDumper.cpp248 case ISD::FADD: return "fadd"; in getOperationName()
H A DTargetLowering.cpp2547 case ISD::FADD: in SimplifyDemandedVectorElts()
5529 case ISD::FADD: in isNegatibleForFree()
5629 case ISD::FADD:
6212 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
6257 Slow = DAG.getNode(ISD::FADD, dl, DstVT, SignCvt, SignCvt);
6270 !isOperationLegalOrCustom(ISD::FADD, DstVT) ||
6303 Result = DAG.getNode(ISD::FADD, dl, DstVT, LoFlt, HiSub);
7611 case ISD::VECREDUCE_FADD: BaseOpcode = ISD::FADD; break;
H A DLegalizeDAG.cpp2483 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
3254 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3258 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
4118 case ISD::FADD:
4446 case ISD::FADD:
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp406 setOperationAction(ISD::FADD, VT, Expand); in AMDGPUTargetLowering()
497 setTargetDAGCombine(ISD::FADD); in AMDGPUTargetLowering()
513 case ISD::FADD: in fnegFoldsIntoOp()
2061 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
2140 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2194 return DAG.getNode(ISD::FADD, SL, VT, T, Sel); in LowerFROUND_LegalFTRUNC()
2288 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2501 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
3688 case ISD::FADD: { in performFNegCombine()
3706 SDValue Res = DAG.getNode(ISD::FADD, S in performFNegCombine()
[all...]
H A DAMDGPUTargetTransformInfo.cpp404 case ISD::FADD: in getArithmeticInstrCost()
H A DSIISelLowering.cpp625 setOperationAction(ISD::FADD, MVT::v2f16, Legal); in SITargetLowering()
652 setOperationAction(ISD::FADD, MVT::v4f16, Custom); in SITargetLowering()
720 setTargetDAGCombine(ISD::FADD); in SITargetLowering()
4099 case ISD::FADD: in LowerOperation()
8592 case ISD::FADD: in fp16SrcZerosHighBits()
8761 case ISD::FADD: in isCanonicalized()
9311 case ISD::FADD: in performExtractVectorEltCombine()
9671 if (LHS.getOpcode() == ISD::FADD) { in performFAddCombine()
9683 if (RHS.getOpcode() == ISD::FADD) { in performFAddCombine()
9714 if (LHS.getOpcode() == ISD::FADD) { in performFSubCombine()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp520 setTargetDAGCombine(ISD::FADD); in NVPTXTargetLowering()
537 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) { in NVPTXTargetLowering()
2116 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, A, PointFiveWithSign); in LowerFROUND32()
2147 SDValue AdjustedA = DAG.getNode(ISD::FADD, SL, VT, AbsA, in LowerFROUND64()
4391 if (User->getOpcode() != ISD::FADD) in PerformADDCombineWithOperands()
4762 case ISD::FADD: in PerformDAGCombine()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dconstants-arm64.h1220 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1221 FADD_s = FADD,
1222 FADD_d = FADD | FP64,
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_target_gv100.cpp150 OPINFO(FADD , R , NA , RIC , NA , NONE, NONE);
/third_party/vixl/src/aarch64/
H A Dconstants-aarch64.h1650 FADD = FPDataProcessing2SourceFixed | 0x00002000, enumerator
1651 FADD_h = FADD | FP16,
1652 FADD_s = FADD,
1653 FADD_d = FADD | FP64,
/third_party/mesa3d/src/broadcom/compiler/
H A Dv3d_compiler.h1319 VIR_A_ALU2(FADD)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1584 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering()
1621 setOperationAction(ISD::FADD, MVT::f64, Legal); in HexagonTargetLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp132 setOperationAction(ISD::FADD, MVT::f16, Promote); in MipsSETargetLowering()
388 setOperationAction(ISD::FADD, Ty, Legal); in addMSAFloatType()
1822 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()

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