| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_inst.h | 127 #define F8(name, gfx4_high, gfx4_low, gfx8_high, gfx8_low, \ macro
254 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108)
260 F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88)
273 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76)
281 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60)
286 F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40)
289 F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36)
290 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50)
291 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
297 F8(flag_subreg_n
1322 #undef F8 global() macro
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 88 PPC::F8 in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
97 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
|
| H A D | PPCISelLowering.cpp | 3317 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3659 PPC::F8 in LowerFormalArguments_32SVR4()
|
| /third_party/typescript/tests/baselines/reference/ |
| H A D | renamingDestructuredPropertyInFunctionType.js | 12 type F8 = ({ a, b: number }) => typeof number; // OK
113 type F8 = ({ a, b: number }: {
|
| /third_party/node/deps/v8/src/codegen/ia32/ |
| H A D | sse-instr.h | 56 V(psubb, 66, 0F, F8) \
|
| /third_party/mbedtls/library/ |
| H A D | aes.c | 119 V(A5, 63, 63, C6), V(84, 7C, 7C, F8), V(99, 77, 77, EE), V(8D, 7B, 7B, F6), \
175 V(38, E1, E1, D9), V(13, F8, F8, EB), V(B3, 98, 98, 2B), V(33, 11, 11, 22), \
179 V(8F, 8C, 8C, 03), V(F8, A1, A1, 59), V(80, 89, 89, 09), V(17, 0D, 0D, 1A), \
258 V(58, 68, 48, 70), V(19, FD, 45, 8F), V(87, 6C, DE, 94), V(B7, F8, 7B, 52), \
270 V(47, 0A, 7C, A1), V(E9, 0F, 42, 7C), V(C9, 1E, 84, F8), V(00, 00, 00, 00), \
282 V(7D, 24, 4A, 85), V(F8, 3D, BB, D2), V(11, 32, F9, AE), V(6D, A1, 29, C7), \
302 V(8C, 61, D7, 9A), V(7A, 0C, A1, 37), V(8E, 14, F8, 59), V(89, 3C, 13, EB), \
|
| /third_party/node/deps/v8/src/codegen/x64/ |
| H A D | sse-instr.h | 98 V(psubb, 66, 0F, F8) \
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 73 SP::F8, SP::F9, SP::F10, SP::F11,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 141 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
|
| /third_party/skia/third_party/externals/microhttpd/doc/ |
| H A D | texinfo.tex | 1569 <1C> <00F8>
1655 <1C> <00F8>
1740 <1C> <00F8>
9332 \DeclareUnicodeCharacter{00F8}{\o}
9479 \DeclareUnicodeCharacter{01F8}{\`N}
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 5395 case Mips::F8: return Mips::T0; in getRegisterForMxtrFP()
|