| /third_party/vixl/benchmarks/aarch64/ |
| H A D | bench-utils.cc | 223 __ Eor(PickR(size), PickR(size), Operand(PickR(size))); in GenerateOperandSequence()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 76 __ Eor(x11, x0, 0x18001); in TEST()
533 __ Eor(w13, w0, kWMinInt); in TEST()
902 __ Eor(x2, x0, Operand(x1)); in TEST()
903 __ Eor(w3, w0, Operand(w1, LSL, 4)); in TEST()
904 __ Eor(x4, x0, Operand(x1, LSL, 4)); in TEST()
905 __ Eor(x5, x0, Operand(x1, LSR, 1)); in TEST()
906 __ Eor(w6, w0, Operand(w1, ASR, 20)); in TEST()
907 __ Eor(x7, x0, Operand(x1, ASR, 20)); in TEST()
908 __ Eor(w8, w0, Operand(w1, ROR, 28)); in TEST()
909 __ Eor(x in TEST()
[all...] |
| H A D | test-disasm-aarch64.cc | 2908 COMPARE_MACRO(Eor(w4, w5, 0), "mov w4, w5"); in TEST()
2909 COMPARE_MACRO(Eor(x4, x5, 0), "mov x4, x5"); in TEST()
2924 COMPARE_MACRO(Eor(w16, w17, 0xffffffff), "mvn w16, w17"); in TEST()
2925 COMPARE_MACRO(Eor(x16, x17, 0xffffffff), "eor x16, x17, #0xffffffff"); in TEST()
2926 COMPARE_MACRO(Eor(x16, x17, 0xffffffffffffffff), "mvn x16, x17"); in TEST()
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| H A D | test-assembler-sve-aarch64.cc | 492 __ Eor(z3.VnD(), z8.VnD(), z15.VnD());
1088 __ Eor(p2.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
1367 __ Eor(z5.VnD(), z5.VnD(), 0x0000ffff0000ffff);
1368 __ Eor(z6.VnS(), z6.VnS(), 0xff0000ff);
1369 __ Eor(z7.VnH(), z7.VnH(), 0x0ff0);
1370 __ Eor(z8.VnB(), z8.VnB(), 0x3f);
4938 fn = &MacroAssembler::Eor;
9914 __ Eor(pg_diff.VnB(), all.Zeroing(), pg_diff.VnB(), pg_ff.VnB());
10494 __ Eor(z4.VnB(), z4.VnB(), z0.VnB());
10498 __ Eor(z
[all...] |
| H A D | test-disasm-neon-aarch64.cc | 1775 COMPARE_MACRO(Eor(v6.V8B(), v7.V8B(), v8.V8B()), "eor v6.8b, v7.8b, v8.8b"); in TEST()
1776 COMPARE_MACRO(Eor(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
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| H A D | test-disasm-sve-aarch64.cc | 2391 COMPARE_MACRO(Eor(z23.VnB(), p4.Merging(), z23.VnB(), z15.VnB()), in TEST()
2393 COMPARE_MACRO(Eor(z23.VnH(), p4.Merging(), z23.VnH(), z15.VnH()), in TEST()
2395 COMPARE_MACRO(Eor(z23.VnD(), p4.Merging(), z18.VnD(), z15.VnD()), in TEST()
5982 COMPARE_MACRO(Eor(z12, z3, z17), "eor z12.d, z3.d, z17.d"); in TEST()
5987 COMPARE_MACRO(Eor(z12.VnH(), z3.VnH(), z17.VnH()), "eor z12.d, z3.d, z17.d"); in TEST()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 3346 COMPARE_T32(Eor(eq, r0, r0, r7), in TEST()
3350 COMPARE_T32(Eor(eq, r0, r0, 0x1), in TEST()
4054 CHECK_T32_16(Eor(DontCare, r7, r7, r6), "eors r7, r6\n"); in TEST()
4056 CHECK_T32_16_IT_BLOCK(Eor(DontCare, eq, r7, r7, r6), in TEST()
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| H A D | test-assembler-aarch32.cc | 3268 __ Eor(r0, r0, 0); in TEST()
3312 __ Eor(r3, r0, 0xffffffff); in TEST()
6014 // CHECK_SIZE_MATCH(Eor(DontCare, r7, r7, r6),
6015 // Eor(DontCare, r7, r6, r7));
6017 // CHECK_SIZE_MATCH(Eor(DontCare, eq, r7, r7, r6),
6018 // Eor(DontCare, eq, r7, r6, r7));
6065 CHECK_SIZE_MATCH(Eor(r7, r7, r6), Eor(r7, r6, r7));
6067 // CHECK_SIZE_MATCH(Eor(eq, r7, r7, r6),
6068 // Eor(e
[all...] |
| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 124 M(Eor) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 124 M(Eor) \
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| H A D | test-simulator-cond-rd-rn-operand-const-a32.cc | 124 M(Eor) \
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| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 124 M(Eor) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 124 M(Eor) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 124 M(Eor) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 124 M(Eor) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 124 M(Eor) \
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 370 V(eor, Eor) \
675 inline void Eor(const Register& rd, const Register& rn,
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| H A D | macro-assembler-arm64-inl.h | 71 void TurboAssembler::Eor(const Register& rd, const Register& rn, in Eor() function in v8::internal::TurboAssembler
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 391 Eor, enumerator
1007 using InstARM32Eor = InstARM32ThreeAddrGPR<InstARM32::Eor>;
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| H A D | IceInstARM32.cpp | 3410 template class InstARM32ThreeAddrGPR<InstARM32::Eor>;
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1385 __ Eor(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction()
1389 __ Eor(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction()
2064 ATOMIC_BINOP_CASE(Xor, Eor) in AssembleArchInstruction()
2632 __ Eor(dst, dst, dst); in AssembleArchInstruction()
2637 SIMD_BINOP_CASE(kArm64S128Xor, Eor, 16B); in AssembleArchInstruction()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 797 void Eor(const Register& rd, const Register& rn, const Operand& operand);
2865 V(eor, Eor) \
3223 V(eor, Eor) \
4244 void Eor(const PRegisterWithLaneSize& pd, in Eor() function in vixl::aarch64::MacroAssembler
4252 void Eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in Eor() function in vixl::aarch64::MacroAssembler
4262 void Eor(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Eor() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.cc | 854 void MacroAssembler::Eor(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1108 I32_BINOP_I(i32_xor, Eor)
1117 I64_BINOP_I(i64_xor, Eor)
2901 Eor(dst.fp().V16B(), lhs.fp().V16B(), rhs.fp().V16B()); in emit_i8x16_bitmask()
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 1947 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1975 void Eor(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1976 Eor(al, rd, rn, operand); in MacroAssembler()
1978 void Eor(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
1985 Eor(cond, rd, rn, operand); in MacroAssembler()
1997 Eor(cond, rd, rn, operand); in MacroAssembler()
2002 void Eor(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
2006 Eor(flags, al, rd, rn, operand); in MacroAssembler()
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