Searched refs:EXTR (Results 1 - 7 of 7) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 71 EXTR,
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| H A D | AArch64ISelLowering.cpp | 1278 case AArch64ISD::EXTR: return "AArch64ISD::EXTR"; in getTargetNodeName()
10084 /// An EXTR instruction is made up of two shifts, ORed together. This helper
10103 /// EXTR instruction extracts a contiguous chunk of bits from two existing
10106 /// with an EXTR. Can't quite be done in TableGen because the two immediates
10132 // not really an EXTR. in tryCombineToEXTR()
10144 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS, in tryCombineToEXTR()
10197 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) in performORCombine()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeARM_64.c | 89 #define EXTR 0x93c00000 macro
752 return push_inst(compiler, (EXTR ^ (inv_bits | (inv_bits >> 9))) | RD(dst) | RN(arg1) | RM(arg1) | ((sljit_ins)imm << 10)); in emit_op_imm()
1529 return push_inst(compiler, (EXTR ^ (inv_bits | (inv_bits >> 9))) | RD(src_dst) in sljit_emit_shift_into()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | constants-arm64.h | 692 EXTR = EXTR_w
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| H A D | assembler-arm64.cc | 1011 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.SizeInBits()) | Rn(rn) | in extr()
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| /third_party/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 844 EXTR = EXTR_w enumerator
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| H A D | assembler-aarch64.cc | 720 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.GetSizeInBits()) | Rn(rn) | in extr()
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