| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMasking.cpp | 69 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
85 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
114 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
275 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
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| H A D | SIFixVGPRCopies.cpp | 58 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) { in runOnMachineFunction()
60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
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| H A D | SIOptimizeExecMaskingPreRA.cpp | 94 MI.modifiesRegister(AMDGPU::EXEC, TRI); in isEndCF()
98 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in isFullExecCopy()
111 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getOrNonExecReg()
199 const unsigned ExecReg = Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in optimizeVcndVcmpPair()
306 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
394 LLVM_DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n'); in runOnMachineFunction()
425 LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n'); in runOnMachineFunction()
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| H A D | SIWholeQuadMode.cpp | 21 /// S_MOV_B64 LiveMask, EXEC
22 /// S_WQM_B64 EXEC, EXEC
29 /// S_MOV_B64 EXEC, Tmp
36 /// S_MOV_B64 EXEC, Tmp
284 if (Reg == AMDGPU::EXEC || Reg == AMDGPU::EXEC_LO) in markInstructionUses()
532 /// execution, they don't care about EXEC.
537 // Skip instructions that are not affected by EXEC in requiresCorrectState()
548 // SGPR instructions are not affected by EXEC in requiresCorrectState()
639 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in toExact()
[all...] |
| H A D | SILowerControlFlow.cpp | 16 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// EXEC to update the predicates.
37 /// // EXEC are zero.
268 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC); in emitIf()
296 .add(MI.getOperand(1)); // Saved EXEC in emitElse()
351 LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC); in emitElse()
461 if (I->modifiesRegister(AMDGPU::EXEC, TRI) && in findMaskOperands()
524 Exec = AMDGPU::EXEC; in runOnMachineFunction()
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| H A D | SIInsertSkips.cpp | 127 // when EXEC = 0. We should skip the loop lest it becomes infinite. in shouldSkip()
135 // These instructions are potentially expensive even if EXEC = 0. in shouldSkip()
276 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in kill()
349 const unsigned ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in optimizeVccBranch()
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| H A D | GCNHazardRecognizer.cpp | 607 // Check for DPP VGPR read after VALU VGPR write and EXEC write. in checkDPPHazards()
625 DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC, IsHazardDefFn, in checkDPPHazards()
1038 if (!MI->modifiesRegister(AMDGPU::EXEC, TRI)) in fixVcmpxExecWARHazard()
1044 return I->readsRegister(AMDGPU::EXEC, TRI); in fixVcmpxExecWARHazard()
1213 getWaitStatesSinceDef(AMDGPU::EXEC, IsVALUFn, MaxWaitStates); in checkMAIHazards()
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| H A D | SIInstrInfo.cpp | 1461 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
1473 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
2737 // Target-independent instructions do not have an implicit-use of EXEC, even
2738 // when they operate on VGPRs. Treating EXEC modifications as scheduling
2741 MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
2769 // when executed with an empty EXEC mask.
2772 // EXEC = 0, but checking for that case here seems not worth it
2786 // However, executing them with EXEC = 0 causes them to operate on undefined
2805 return MI.readsRegister(AMDGPU::EXEC, &RI);
2816 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC,
[all...] |
| H A D | SIFrameLowering.cpp | 745 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitPrologue()
903 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitEpilogue()
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| H A D | AMDGPUInstructionSelector.cpp | 318 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in selectG_ADD_SUB()
409 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in selectG_UADDO_USUBO_UADDE_USUBE()
1628 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
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| H A D | SILowerI1Copies.cpp | 473 ExecReg = AMDGPU::EXEC;
849 // TODO: check whether CurReg is already masked by EXEC
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| H A D | AMDGPUAsmPrinter.cpp | 708 case AMDGPU::EXEC: in analyzeResourceUsage()
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| H A D | SIFoldOperands.cpp | 1138 // uses of EXEC, but adding them invalidates the use_iterator, so defer in foldInstOperand()
1228 // Make sure we add EXEC uses to any new v_mov instructions created. in foldInstOperand()
1237 if (DefMI->readsRegister(AMDGPU::EXEC, TRI) && in foldInstOperand()
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| H A D | SIInsertWaitcnts.cpp | 933 // Export & GDS instructions do not read the EXEC mask until after the export in generateWaitcntInstBefore()
936 // before overwriting the EXEC mask. in generateWaitcntInstBefore()
938 if (MI.modifiesRegister(AMDGPU::EXEC, TRI)) { in generateWaitcntInstBefore()
940 // for EXEC. in generateWaitcntInstBefore()
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| /third_party/elfutils/backends/ |
| H A D | common-reloc.c | 73 #define EXEC (1 << (ET_EXEC - 1)) macro
82 #undef EXEC macro
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| /third_party/rust/crates/rustix/src/backend/linux_raw/mm/ |
| H A D | types.rs | 16 const EXEC = linux_raw_sys::general::PROT_EXEC; consts
32 const EXEC = linux_raw_sys::general::PROT_EXEC; consts
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| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| H A D | nvc0_transfer.c | 98 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1); in nvc0_m2mf_transfer_rect()
192 BEGIN_NVC0(push, NVE4_COPY(EXEC), 1); in nve4_m2mf_transfer_rect()
224 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1); in nvc0_m2mf_push_linear()
306 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1); in nvc0_m2mf_copy_linear()
339 BEGIN_NVC0(push, NVE4_COPY(EXEC), 1); in nve4_m2mf_copy_linear()
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| /third_party/rust/crates/rustix/src/backend/libc/mm/ |
| H A D | types.rs | 16 const EXEC = c::PROT_EXEC; consts
32 const EXEC = c::PROT_EXEC; consts
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| /third_party/mesa3d/src/freedreno/ir2/ |
| H A D | instr-a2xx.h | 182 EXEC = 1, enumerator
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| H A D | disasm-a2xx.c | 500 return (cf->opc == EXEC) || (cf->opc == EXEC_END) || in cf_exec()
581 INSTR(EXEC, print_cf_exec),
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| H A D | ir2_assemble.c | 368 instr_cf_exec_t exec = {.opc = EXEC}; in assemble()
522 case EXEC: in assemble()
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| H A D | fd2_gmem.c | 573 /* patch out unneeded memory exports by changing EXEC CF to EXEC_END
576 * a specific pattern of ALLOC/EXEC CF pairs for the hw binning exports
586 assert(cf->opc == EXEC);
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| /third_party/littlefs/ |
| H A D | Makefile | 139 ifdef EXEC
140 TESTFLAGS += --exec="$(EXEC)"
141 BENCHFLAGS += --exec="$(EXEC)"
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| /third_party/mesa3d/src/gallium/drivers/nouveau/ |
| H A D | nouveau_video.c | 94 BEGIN_NV04(push, NV31_MPEG(EXEC), 1); in nouveau_vpe_fini()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 1089 case 126: return createRegOperand(EXEC);
|