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Searched refs:DstReg (Results 1 - 25 of 137) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program_tex.c68 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in scale_texcoords()
69 inst_mov->U.I.DstReg.Index = temp; in scale_texcoords()
90 inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
91 inst_rcp->U.I.DstReg.Index = temp; in projective_divide()
92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in projective_divide()
101 inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY; in projective_divide()
102 inst_mul->U.I.DstReg.Index = temp; in projective_divide()
164 struct rc_dst_register output_reg = inst->U.I.DstReg; in radeonTransformTEX()
170 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; in radeonTransformTEX()
171 inst->U.I.DstReg in radeonTransformTEX()
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H A Dr3xx_vertprog.c196 t_dst_index(vp, &vpi->DstReg), in ei_vector1()
197 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector1()
198 t_dst_class(vpi->DstReg.File), in ei_vector1()
213 t_dst_index(vp, &vpi->DstReg), in ei_vector2()
214 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector2()
215 t_dst_class(vpi->DstReg.File), in ei_vector2()
230 t_dst_index(vp, &vpi->DstReg), in ei_math1()
231 t_dst_mask(vpi->DstReg.WriteMask), in ei_math1()
232 t_dst_class(vpi->DstReg.File), in ei_math1()
248 t_dst_index(vp, &vpi->DstReg), in ei_lit()
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H A Dradeon_compiler.c133 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT) in rc_calculate_inputs_outputs()
134 c->Program.OutputsWritten |= 1U << inst->U.I.DstReg.Index; in rc_calculate_inputs_outputs()
168 if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) { in rc_copy_output()
170 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; in rc_copy_output()
171 inst->U.I.DstReg.Index = tempreg; in rc_copy_output()
184 last_write_inst->U.I.DstReg.File = RC_FILE_OUTPUT; in rc_copy_output()
185 last_write_inst->U.I.DstReg.Index = output; in rc_copy_output()
193 inst->U.I.DstReg.Index = dup_output; in rc_copy_output()
197 inst->U.I.DstReg in rc_copy_output()
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H A Dradeon_pair_translate.c92 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; in classify_instruction()
93 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; in classify_instruction()
277 inst->DstReg.WriteMask); in set_pair_instruction()
286 if (inst->DstReg.File == RC_FILE_OUTPUT) { in set_pair_instruction()
287 if (inst->DstReg.Index == c->OutputDepth) { in set_pair_instruction()
288 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
291 if (inst->DstReg.Index == c->OutputColor[i]) { in set_pair_instruction()
295 inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
297 GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
304 pair->RGB.DestIndex = inst->DstReg in set_pair_instruction()
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H A Dradeon_program_alu.c46 struct rc_dst_register DstReg, struct rc_src_register SrcReg) in emit1()
55 fpi->U.I.DstReg = DstReg; in emit1()
63 struct rc_dst_register DstReg, in emit2()
73 fpi->U.I.DstReg = DstReg; in emit2()
82 struct rc_dst_register DstReg, in emit3()
93 fpi->U.I.DstReg = DstReg; in emit3()
205 if (inst->U.I.DstReg in is_dst_safe_to_reuse()
43 emit1( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg) emit1() argument
60 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) emit2() argument
79 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) emit3() argument
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H A Dradeon_emulate_branches.c76 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in handle_if()
77 inst_mov->U.I.DstReg.Index = rc_find_free_temporary(s->C); in handle_if()
78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; in handle_if()
82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index; in handle_if()
166 inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY; in allocate_and_insert_proxies()
167 inst_mov->U.I.DstReg.Index = proxies->Temporary[index].Index; in allocate_and_insert_proxies()
168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in allocate_and_insert_proxies()
185 inst_cmp->U.I.DstReg.File = file; in inject_cmp()
186 inst_cmp->U.I.DstReg.Index = index; in inject_cmp()
187 inst_cmp->U.I.DstReg in inject_cmp()
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H A Dradeon_vert_fc.c129 build_pred_dst(&new_inst->U.I.DstReg, fc_state); in lower_bgnloop()
149 build_pred_dst(&new_inst->U.I.DstReg, fc_state); in lower_bgnloop()
163 inst->U.I.DstReg.Pred = RC_PRED_SET; in lower_brk()
169 inst->U.I.DstReg.Pred = RC_PRED_SET; in lower_brk()
172 build_pred_dst(&inst->U.I.DstReg, fc_state); in lower_brk()
183 build_pred_dst(&new_inst->U.I.DstReg, fc_state); in lower_endloop()
219 build_pred_dst(&inst->U.I.DstReg, fc_state); in lower_if()
262 build_pred_dst(&inst->U.I.DstReg, &fc_state); in rc_vert_fc()
272 build_pred_dst(&inst->U.I.DstReg, &fc_state); in rc_vert_fc()
279 inst->U.I.DstReg in rc_vert_fc()
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H A Dr3xx_fragprog.c49 if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth) in rc_rewrite_depth_out()
52 if (inst->DstReg.WriteMask & RC_MASK_Z) { in rc_rewrite_depth_out()
53 inst->DstReg.WriteMask = RC_MASK_W; in rc_rewrite_depth_out()
55 inst->DstReg.WriteMask = 0; in rc_rewrite_depth_out()
/third_party/mesa3d/src/mesa/program/
H A Dprogramopt.c90 newInst[i].DstReg.File = PROGRAM_OUTPUT; in insert_mvp_dp4_code()
91 newInst[i].DstReg.Index = VARYING_SLOT_POS; in insert_mvp_dp4_code()
92 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); in insert_mvp_dp4_code()
161 newInst[0].DstReg.File = PROGRAM_TEMPORARY; in insert_mvp_mad_code()
162 newInst[0].DstReg.Index = hposTemp; in insert_mvp_mad_code()
163 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
173 newInst[i].DstReg.File = PROGRAM_TEMPORARY; in insert_mvp_mad_code()
174 newInst[i].DstReg.Index = hposTemp; in insert_mvp_mad_code()
175 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; in insert_mvp_mad_code()
188 newInst[3].DstReg in insert_mvp_mad_code()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp69 unsigned DstReg) { in buildMI()
70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); in buildMI()
145 Register DstReg = MI.getOperand(0).getReg();
152 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
178 Register DstReg = MI.getOperand(0).getReg(); in expandLogic() local
185 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
225 Register DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
232 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
277 unsigned DstReg = MI.getOperand(0).getReg(); in expand() local
281 TRI->splitReg(DstReg, DstLoRe in expand()
68 buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode, unsigned DstReg) buildMI() argument
329 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
392 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
422 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
455 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
490 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
539 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
583 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
632 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
663 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
694 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
749 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1018 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1046 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1080 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1114 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1149 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1234 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1257 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1294 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1338 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1371 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1414 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1457 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1511 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
1540 unsigned DstReg = MI.getOperand(0).getReg(); expand() local
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H A DAVRRegisterInfo.cpp98 static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, unsigned DstReg) { in foldFrameOffset() argument
107 // Check that DstReg matches with next instruction, otherwise the instruction in foldFrameOffset()
109 if (DstReg != MI.getOperand(0).getReg()) { in foldFrameOffset()
161 Register DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
162 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); in eliminateFrameIndex()
175 foldFrameOffset(II, Offset, DstReg); in eliminateFrameIndex()
177 // Select the best opcode based on DstReg and the offset size. in eliminateFrameIndex()
178 switch (DstReg) { in eliminateFrameIndex()
196 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg) in eliminateFrameIndex()
197 .addReg(DstReg, RegStat in eliminateFrameIndex()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h54 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt() local
61 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); in tryCombineAnyExt()
62 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
74 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
75 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
84 const LLT &DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
88 DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits())); in tryCombineAnyExt()
89 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
103 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt() local
109 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
147 Register DstReg = MI.getOperand(0).getReg(); tryCombineSExt() local
174 Register DstReg = MI.getOperand(0).getReg(); tryCombineTrunc() local
206 Register DstReg = MI.getOperand(0).getReg(); tryFoldImplicitDef() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp108 const unsigned DstReg,
121 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
124 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
233 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
234 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
241 if (Register::isPhysicalRegister(DstReg)) { in selectCopy()
249 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy()
278 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
296 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
690 selectTurnIntoCOPY( MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg, const TargetRegisterClass *DstRC, const unsigned SrcReg, const TargetRegisterClass *SrcRC) const selectTurnIntoCOPY() argument
712 const Register DstReg = I.getOperand(0).getReg(); selectTruncOrPtrToInt() local
776 const Register DstReg = I.getOperand(0).getReg(); selectZext() local
887 const Register DstReg = I.getOperand(0).getReg(); selectAnyext() local
1084 const Register DstReg = I.getOperand(0).getReg(); selectUadde() local
1144 const Register DstReg = I.getOperand(0).getReg(); selectExtract() local
1195 emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const emitExtractSubreg() argument
1233 emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const emitInsertSubreg() argument
1276 const Register DstReg = I.getOperand(0).getReg(); selectInsert() local
1361 Register DstReg = I.getOperand(0).getReg(); selectMergeValues() local
1435 const Register DstReg = I.getOperand(0).getReg(); materializeFP() local
1496 Register DstReg = I.getOperand(0).getReg(); selectImplicitDefOrPHI() local
1527 const Register DstReg = I.getOperand(0).getReg(); selectDivRem() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
202 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
206 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
220 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
222 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
241 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
243 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
251 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
253 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
261 DstReg in getDuplexCandidateGroup()
542 unsigned DstReg, SrcReg; subInstWouldBeExtended() local
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H A DHexagonMCCompound.cpp80 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
96 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
99 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
110 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
112 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
122 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
124 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getCompoundCandidateGroup()
132 DstReg in getCompoundCandidateGroup()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp98 Register DstReg = Dst.getReg(); in selectCOPY() local
101 if (isVCC(DstReg, *MRI)) { in selectCOPY()
107 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
112 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
129 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg) in selectCOPY()
141 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
210 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64() local
215 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg) in getSubOperand64()
218 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(), in getSubOperand64()
255 Register DstReg in selectG_AND_OR_XOR() local
296 Register DstReg = I.getOperand(0).getReg(); selectG_ADD_SUB() local
450 Register DstReg = I.getOperand(0).getReg(); selectG_EXTRACT() local
487 Register DstReg = MI.getOperand(0).getReg(); selectG_MERGE_VALUES() local
588 Register DstReg = I.getOperand(0).getReg(); selectG_INSERT() local
651 Register DstReg = I.getOperand(0).getReg(); selectG_INTRINSIC() local
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H A DSILowerI1Copies.cpp95 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
510 Register DstReg = MI.getOperand(0).getReg();
515 if (isLaneMaskReg(DstReg) || isVreg1(DstReg))
522 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));
526 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
570 Register DstReg = MI->getOperand(0).getReg();
571 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass
596 PhiRegisters.insert(DstReg);
602 for (MachineInstr &Use : MRI->use_instructions(DstReg))
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H A DR600ExpandSpecialInstrs.cpp138 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
139 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
142 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
208 Register DstReg = in runOnMachineFunction() local
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
242 Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
243 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
244 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
264 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src in runOnMachineFunction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp57 MachineInstr &MI, Register &SrcReg, Register &DstReg,
59 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
147 Register &DstReg, const GlobalValue *GVal) { in processCandidate()
148 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
155 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
165 processDstReg(MRI, TmpReg, DstReg, GVal, false); in processCandidate()
169 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg) in processCandidate()
174 // All uses of DstReg replaced by SrcReg in processCandidate()
175 processDstReg(MRI, DstReg, SrcReg, GVal, true); in processCandidate()
179 Register &DstReg, Registe in processDstReg()
145 processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB, MachineInstr &MI, Register &SrcReg, Register &DstReg, const GlobalValue *GVal) processCandidate() argument
178 processDstReg(MachineRegisterInfo *MRI, Register &DstReg, Register &SrcReg, const GlobalValue *GVal, bool doSrcRegProp) processDstReg() argument
254 Register DstReg = MI.getOperand(0).getReg(); removeLD() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp139 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
142 if (Register::isVirtualRegister(DstReg) && in runOnMachineFunction()
147 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
160 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
162 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
177 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
179 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
188 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
191 if (Register::isVirtualRegister(DstReg) && in runOnMachineFunction()
196 PeepholeMap[DstReg] in runOnMachineFunction()
211 Register DstReg = Dst.getReg(); runOnMachineFunction() local
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/third_party/mesa3d/src/gallium/drivers/r300/compiler/tests/
H A Drc_test_helpers.c290 inst->U.I.DstReg.File = RC_FILE_TEMPORARY; in init_rc_normal_dst()
292 inst->U.I.DstReg.File = RC_FILE_OUTPUT; in init_rc_normal_dst()
294 inst->U.I.DstReg.File = RC_FILE_NONE; in init_rc_normal_dst()
303 inst->U.I.DstReg.Index = strtol(tokens.Index.String, NULL, 10); in init_rc_normal_dst()
312 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in init_rc_normal_dst()
314 inst->U.I.DstReg.WriteMask = 0; in init_rc_normal_dst()
323 inst->U.I.DstReg.WriteMask |= RC_MASK_X; in init_rc_normal_dst()
326 inst->U.I.DstReg.WriteMask |= RC_MASK_Y; in init_rc_normal_dst()
329 inst->U.I.DstReg.WriteMask |= RC_MASK_Z; in init_rc_normal_dst()
332 inst->U.I.DstReg in init_rc_normal_dst()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp164 void scanUses(unsigned DstReg);
408 unsigned &SrcReg, unsigned &DstReg, in isCopyToReg()
411 DstReg = 0; in isCopyToReg()
413 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
416 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
422 IsDstPhys = Register::isPhysicalRegister(DstReg); in isCopyToReg()
491 unsigned SrcReg, DstReg; in isKilled() local
494 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
502 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { in isTwoAddrUse() argument
509 DstReg in isTwoAddrUse()
407 isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys) isCopyToReg() argument
519 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) findOnlyInterestingUse() argument
773 scanUses(unsigned DstReg) scanUses() argument
834 unsigned SrcReg, DstReg; processCopy() local
895 unsigned DstReg; rescheduleMIBelowKill() local
1080 unsigned DstReg; rescheduleKillAboveMI() local
1475 Register DstReg = DstMO.getReg(); collectTiedOperands() local
1743 Register DstReg = mi->getOperand(DstIdx).getReg(); runOnMachineFunction() local
1801 Register DstReg = MI.getOperand(0).getReg(); eliminateRegSequence() local
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H A DRegisterCoalescer.cpp214 /// Attempt to join intervals corresponding to SrcReg/DstReg, which are the
284 /// Replace all defs and uses of SrcReg to DstReg and update the subregister
285 /// number if it is not zero. If DstReg is a physical register and the
288 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
427 SrcReg = DstReg = 0; in setRegisters()
479 // SrcReg will be merged with a sub-register of DstReg. in setRegisters()
483 // DstReg will be merged with a sub-register of SrcReg. in setRegisters()
495 // Prefer SrcReg to be a sub-register of DstReg. in setRegisters()
510 DstReg = Dst; in setRegisters()
515 if (Register::isPhysicalRegister(DstReg)) in flip()
1239 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg(); reMaterializeTrivialDef() local
1555 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; eliminateUndefCopy() local
1680 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) updateRegDefsUses() argument
1922 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg(); joinCopy() local
2014 unsigned DstReg = CP.getDstReg(); joinReservedPhysReg() local
3646 Register DstReg = Copy->getOperand(0).getReg(); isLocalCopy() local
3690 isTerminalReg(unsigned DstReg, const MachineInstr &Copy, const MachineRegisterInfo *MRI) isTerminalReg() argument
3704 unsigned DstReg, DstSubReg, SrcReg, SrcSubReg; applyTerminalRule() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp186 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock()
195 SrcReg != DstReg) { in knownRegValInBlock()
209 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
214 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
218 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
252 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
253 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
258 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp195 void LegalizerHelper::insertParts(Register DstReg, in insertParts() argument
204 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
209 MIRBuilder.buildConcatVectors(DstReg, PartRegs); in insertParts()
211 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
232 DstReg : MRI.createGenericVirtualRegister(ResultTy); in insertParts()
620 Register DstReg = MI.getOperand(0).getReg(); in narrowScalar() local
621 if(MRI.getType(DstReg).isVector()) in narrowScalar()
622 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
624 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
733 Register DstReg in narrowScalar() local
746 Register DstReg = MI.getOperand(0).getReg(); narrowScalar() local
766 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); narrowScalar() local
795 Register DstReg = MI.getOperand(0).getReg(); narrowScalar() local
814 Register DstReg = MI.getOperand(0).getReg(); narrowScalar() local
1073 Register DstReg = MI.getOperand(0).getReg(); narrowScalar() local
1340 Register DstReg = MI.getOperand(0).getReg(); widenScalarExtract() local
1514 Register DstReg = MI.getOperand(0).getReg(); widenScalar() local
1540 Register DstReg = MI.getOperand(0).getReg(); widenScalar() local
2074 Register DstReg = MI.getOperand(0).getReg(); lower() local
2297 Register DstReg = MI.getOperand(0).getReg(); lower() local
2330 Register DstReg = MI.getOperand(0).getReg(); fewerElementsVectorImplicitDef() local
2359 const Register DstReg = MI.getOperand(0).getReg(); fewerElementsVectorBasic() local
2423 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); fewerElementsVectorBasic() local
2468 const Register DstReg = MI.getOperand(0).getReg(); fewerElementsVectorMultiEltType() local
2573 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); fewerElementsVectorCasts() local
2594 Register DstReg = MI.getOperand(0).getReg(); fewerElementsVectorCmp() local
2637 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); fewerElementsVectorCmp() local
2661 Register DstReg = MI.getOperand(0).getReg(); fewerElementsVectorSelect() local
2715 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); fewerElementsVectorSelect() local
2733 const Register DstReg = MI.getOperand(0).getReg(); fewerElementsVectorPhi() local
3183 Register DstReg = MI.getOperand(0).getReg(); narrowScalarShift() local
3463 Register DstReg = MI.getOperand(0).getReg(); narrowScalarMul() local
3552 Register DstReg = MI.getOperand(0).getReg(); narrowScalarExtract() local
3621 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); narrowScalarInsert() local
3627 Register DstReg = MI.getOperand(0).getReg(); narrowScalarInsert() local
3639 Register DstReg = MI.getOperand(0).getReg(); narrowScalarBasic() local
4125 Register DstReg = MI.getOperand(0).getReg(); lowerFMad() local
4138 Register DstReg = MI.getOperand(0).getReg(); lowerIntrinsicRound() local
4198 Register DstReg = MI.getOperand(0).getReg(); lowerShuffleVector() local
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