Searched refs:Divu (Results 1 - 9 of 9) sorted by relevance
| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | macro-assembler-mips64.h | 439 DEFINE_INSTRUCTION(Divu)
459 DEFINE_INSTRUCTION2(Divu)
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| H A D | macro-assembler-mips64.cc | 706 void TurboAssembler::Divu(Register rs, const Operand& rt) { in CallRecordWriteStub() function in v8::internal::TurboAssembler
719 void TurboAssembler::Divu(Register res, Register rs, const Operand& rt) { in CallRecordWriteStub() function in v8::internal::TurboAssembler
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | macro-assembler-mips.h | 434 DEFINE_INSTRUCTION(Divu)
442 DEFINE_INSTRUCTION2(Divu)
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| H A D | macro-assembler-mips.cc | 665 void TurboAssembler::Divu(Register rs, const Operand& rt) { in CallRecordWriteStub() function in v8::internal::TurboAssembler
678 void TurboAssembler::Divu(Register res, Register rs, const Operand& rt) { in CallRecordWriteStub() function in v8::internal::TurboAssembler
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstMIPS32.h | 224 Divu, enumerator
1231 using InstMIPS32Divu = InstMIPS32ThreeAddrGPR<InstMIPS32::Divu>;
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| /third_party/node/deps/v8/src/wasm/baseline/mips/ |
| H A D | liftoff-assembler-mips.h | 943 TurboAssembler::Divu(dst, lhs, rhs); in emit_i32_divu()
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| /third_party/node/deps/v8/src/wasm/baseline/mips64/ |
| H A D | liftoff-assembler-mips64.h | 1134 TurboAssembler::Divu(dst, lhs, rhs); in emit_i32_divu()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | code-generator-mips64.cc | 984 __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | code-generator-mips.cc | 1014 __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); in AssembleArchInstruction()
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