Home
last modified time | relevance | path

Searched refs:Defs (Results 1 - 25 of 61) sorted by relevance

123

/third_party/lzma/CPP/7zip/Archive/7z/
H A D7zItem.h95 CBoolVector Defs; member
100 Defs.ClearAndSetSize(newSize); in ClearAndSetSize()
106 Defs.Clear(); in Clear()
112 Defs.ReserveDown(); in ReserveDown()
118 if (index < Defs.Size() && Defs[index]) in GetItem()
127 bool ValidAndDefined(unsigned i) const { return i < Defs.Size() && Defs[i]; } in ValidAndDefined()
129 bool CheckSize(unsigned size) const { return Defs.Size() == size || Defs
142 CBoolVector Defs; global() member
[all...]
H A D7zOut.cpp324 const unsigned numDefined = BoolVector_CountSum(digests.Defs); in WriteHashDigests()
329 if (numDefined == digests.Defs.Size()) in WriteHashDigests()
334 WriteBoolVector(digests.Defs); in WriteHashDigests()
337 for (unsigned i = 0; i < digests.Defs.Size(); i++) in WriteHashDigests()
338 if (digests.Defs[i]) in WriteHashDigests()
432 digests2.Defs.Add(digests.Defs[digestIndex]); in WriteSubStreamsInfo()
482 const unsigned numDefined = BoolVector_CountSum(v.Defs); in WriteUInt64DefVector()
486 WriteAlignedBools(v.Defs, numDefined, type, 3); in WriteUInt64DefVector()
488 for (unsigned i = 0; i < v.Defs in WriteUInt64DefVector()
[all...]
H A D7zIn.cpp666 const unsigned numItems = v.Defs.Size(); in Read_UInt32_Vector()
669 const bool *defs = &v.Defs[0]; in Read_UInt32_Vector()
682 ReadBoolVector2(numItems, crcs.Defs); in ReadHashDigests()
994 digests.Defs[k] = true; in ReadSubStreamsInfo()
1001 digests.Defs[k] = defined; in ReadSubStreamsInfo()
1017 if (digests.Defs.Size() != unpackSizes.Size()) in ReadSubStreamsInfo()
1026 digests.Defs[k] = true; in ReadSubStreamsInfo()
1032 digests.Defs[k] = false; in ReadSubStreamsInfo()
1083 /* If digests.Defs.Size() == 0, it means that there are no crcs. in ReadStreamsInfo()
1086 // BoolVector_Fill_False(digests.Defs, folder in ReadStreamsInfo()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in TrackDefUses() argument
106 InsertUsesDefs(LocalDefs, Defs); in TrackDefUses()
138 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock()
152 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
196 RegisterSet Defs, Uses; in InsertITInstructions() local
209 Defs.clear(); in InsertITInstructions()
211 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
262 TrackDefUses(NMI, Defs, Use in InsertITInstructions()
136 MoveCopyOutOfITBlock(MachineInstr *MI, ARMCC::CondCodes CC, ARMCC::CondCodes OCC, RegisterSet &Defs, RegisterSet &Uses) MoveCopyOutOfITBlock() argument
[all...]
H A DA15SDOptimizer.cpp401 SmallVector<unsigned, 8> Defs; in getReadDPRs()
410 Defs.push_back(MO.getReg()); in getReadDPRs()
412 return Defs; in getReadDPRs()
594 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); in runOnInstruction() local
597 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end(); in runOnInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp67 bool canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
69 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
70 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
209 RegUse &Defs, RegUse &Uses) const { in canBundle()
226 RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
265 RegUse &Defs, RegUse &Uses) const { in collectRegUses()
276 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
293 RegUse &Defs, RegUse &Uses, in processRegUses()
295 if (!canBundle(MI, Defs, Uses)) in processRegUses()
301 collectRegUses(MI, Defs, Use in processRegUses()
208 canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const canBundle() argument
264 collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const collectRegUses() argument
292 processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses, GCNDownwardRPTracker &RPT) processRegUses() argument
337 RegUse Defs, Uses; runOnMachineFunction() local
[all...]
H A DSIFixSGPRCopies.cpp454 auto &Defs = Init.second;
456 for (auto I1 = Defs.begin(), E = Defs.end(); I1 != E; ) {
546 auto &Defs = Init.second;
547 auto I = Defs.begin();
548 while (I != Defs.end()) {
551 I = Defs.erase(I);
559 auto &Defs = Init.second;
560 for (auto MI : Defs) {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; member
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
165 expandReg(*R++, Defs); in getDefsUses()
175 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
184 BitVector Defs(NR), Uses(NR); in buildMaps()
189 Defs.reset(); in buildMaps()
191 getDefsUses(MI, Defs, Uses); in buildMaps()
192 DUM.insert(std::make_pair(Index, DefUseInfo(Defs, Use in buildMaps()
[all...]
H A DHexagonExpandCondsets.cpp222 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
391 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs, in updateDeadsInRange()
393 for (MachineBasicBlock *D : Defs) in updateDeadsInRange()
401 if (Defs.count(B)) in updateDeadsInRange()
414 SetVector<MachineBasicBlock*> Defs; in updateDeadsInRange() local
420 Defs.insert(DefI->getParent()); in updateDeadsInRange()
455 if (Dominate(Defs, BB)) in updateDeadsInRange()
791 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
794 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, in canMoveOver() argument
797 // "Defs" an in canMoveOver()
968 ReferenceMap Uses, Defs; predicate() local
[all...]
H A DHexagonBitSimplify.cpp201 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
271 RegisterSet Defs; in visitBlock() local
273 getInstrDefs(I, Defs); in visitBlock()
275 NewAVs.insert(Defs); in visitBlock()
290 RegisterSet &Defs) { in getInstrDefs()
297 Defs.insert(R); in getInstrDefs()
1461 RegisterSet Defs;
1466 Defs.clear();
1467 HBS::getInstrDefs(*I, Defs);
1468 if (Defs
289 getInstrDefs(const MachineInstr &MI, RegisterSet &Defs) getInstrDefs() argument
[all...]
H A DHexagonRDFOpt.cpp256 NodeList Defs; in rewrite() local
261 Defs = DFG.getRelatedRefs(IA, DA); in rewrite()
262 if (!llvm::all_of(Defs, IsDead)) in rewrite()
267 // Mark all nodes in Defs for removal. in rewrite()
268 for (auto D : Defs) in rewrite()
H A DRDFLiveness.cpp158 SetVector<NodeId> Defs; in getAllReachingDefs() local
164 Defs.insert(TA.Id); in getAllReachingDefs()
226 auto DefInSet = [&Defs] (NodeAddr<RefNode*> TA) -> bool { in getAllReachingDefs()
228 Defs.count(TA.Id); in getAllReachingDefs()
270 NodeSet &Visited, const NodeSet &Defs) { in getAllReachingDefsRec()
271 return getAllReachingDefsRecImpl(RefRR, RefA, Visited, Defs, 0, MaxRecNest); in getAllReachingDefsRec()
276 NodeSet &Visited, const NodeSet &Defs, unsigned Nest, unsigned MaxNest) { in getAllReachingDefsRecImpl()
282 for (NodeId D : Defs) { in getAllReachingDefsRecImpl()
290 return { Defs, true }; in getAllReachingDefsRecImpl()
293 NodeSet TmpDefs = Defs; in getAllReachingDefsRecImpl()
269 getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) getAllReachingDefsRec() argument
275 getAllReachingDefsRecImpl(RegisterRef RefRR, NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs, unsigned Nest, unsigned MaxNest) getAllReachingDefsRecImpl() argument
[all...]
H A DHexagonBlockRanges.cpp313 RegisterSet Defs, Clobbers; in computeInitialLiveRanges() local
334 Defs.clear(); in computeInitialLiveRanges()
346 Defs.insert(S); in computeInitialLiveRanges()
365 if (!Defs.count(R)) in computeInitialLiveRanges()
369 // Defs and clobbers can overlap, e.g. in computeInitialLiveRanges()
371 for (RegisterRef R : Defs) in computeInitialLiveRanges()
375 for (RegisterRef S : Defs) { in computeInitialLiveRanges()
376 // Defs should already be expanded into subregs. in computeInitialLiveRanges()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp73 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
76 Defs.insert(V); in findAllDefs()
85 if (Defs.insert(Op).second) in findAllDefs()
88 return Defs; in findAllDefs()
220 auto Defs = findAllDefs(U); in runOnUse() local
223 if (llvm::none_of(Defs, isa<Instruction, Value *>)) in runOnUse()
229 for (Value *V : Defs) in runOnUse()
234 for (Value *V : Defs) in runOnUse()
245 for (Value *V : Defs) in runOnUse()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp153 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); in getPreviousDefInBlock() local
156 if (Defs) { in getPreviousDefInBlock()
161 if (Iter != Defs->rend()) in getPreviousDefInBlock()
169 // Note that if MA comes before Defs->begin(), we won't hit a def. in getPreviousDefInBlock()
180 auto *Defs = MSSA->getWritableBlockDefs(BB); in getPreviousDefFromEnd() local
182 if (Defs) { in getPreviousDefFromEnd()
183 CachedPreviousDef.insert({BB, &*Defs->rbegin()}); in getPreviousDefFromEnd()
184 return &*Defs->rbegin(); in getPreviousDefFromEnd()
261 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); in insertUse() local
262 (void)Defs; in insertUse()
460 auto *Defs = MSSA->getWritableBlockDefs(NewDef->getBlock()); fixupDefs() local
1201 auto *Defs = MSSA->getWritableBlockDefs(From); moveAllAccesses() local
[all...]
H A DMemorySSA.cpp533 auto *Defs = MSSA.getBlockDefs(Node->getBlock()); in getWalkTarget() local
534 if (Defs) in getWalkTarget()
535 return &*Defs->rbegin(); in getWalkTarget()
1526 DefsList *Defs = nullptr; in buildMemorySSA() local
1537 if (!Defs) in buildMemorySSA()
1538 Defs = getOrCreateDefsList(&B); in buildMemorySSA()
1539 Defs->push_back(*MUD); in buildMemorySSA()
1604 auto *Defs = getOrCreateDefsList(BB); in insertIntoListsForBlock() local
1605 Defs->push_front(*NewAccess); in insertIntoListsForBlock()
1611 auto *Defs in insertIntoListsForBlock() local
1620 auto *Defs = getOrCreateDefsList(BB); insertIntoListsForBlock() local
1633 auto *Defs = getOrCreateDefsList(BB); insertIntoListsBefore() local
1842 std::unique_ptr<DefsList> &Defs = DefsIt->second; removeFromLists() local
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
45 Defs[Hexagon::LC0].insert(Unconditional); in init()
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
49 Defs[Hexagon::LC1].insert(Unconditional); in init()
124 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
176 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
384 if (!Defs.count(P) || LatePreds.count(P)) { in checkPredicates()
397 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
496 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly() local
497 for (unsigned j = 0; j < Defs; in checkRegistersReadOnly()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef()
483 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
487 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs()
488 while (!Defs.empty()) { in UpdatePhysRegDefs()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
490 Defs.pop_back(); in UpdatePhysRegDefs()
501 SmallVectorImpl<unsigned> &Defs) { in runOnInstr()
559 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
561 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
566 SmallVector<unsigned, 4> Defs; in runOnBlock() local
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVectorImpl<unsigned> &Defs) HandlePhysRegDef() argument
486 UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs) UpdatePhysRegDefs() argument
500 runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs) runOnInstr() argument
768 DenseSet<unsigned> Defs, Kills; addNewBlock() local
[all...]
H A DMachineInstrBundle.cpp147 SmallVector<MachineOperand*, 4> Defs; in finalizeBundle() local
154 Defs.push_back(&MO); in finalizeBundle()
179 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in finalizeBundle()
180 MachineOperand &MO = *Defs[i]; in finalizeBundle()
207 Defs.clear(); in finalizeBundle()
/third_party/lzma/C/
H A D7z.h64 Byte *Defs; /* MSB 0 bit numbering */ member
70 Byte *Defs; /* MSB 0 bit numbering */ member
77 #define SzBitWithVals_Check(p, i) ((p)->Defs && ((p)->Defs[(i) >> 3] & (0x80 >> ((i) & 7))) != 0)
H A D7zArcIn.c62 #define SzBitUi32s_INIT(p) { (p)->Defs = NULL; (p)->Vals = NULL; }
68 p->Defs = NULL; in SzBitUi32s_Alloc()
73 MY_ALLOC(Byte, p->Defs, (num + 7) >> 3, alloc) in SzBitUi32s_Alloc()
81 ISzAlloc_Free(alloc, p->Defs); p->Defs = NULL; in SzBitUi32s_Free()
85 #define SzBitUi64s_INIT(p) { (p)->Defs = NULL; (p)->Vals = NULL; }
89 ISzAlloc_Free(alloc, p->Defs); p->Defs = NULL; in SzBitUi64s_Free()
356 defs = crcs->Defs; in ReadUi32s()
372 RINOK(ReadBitVector(sd, numItems, &crcs->Defs, allo in ReadBitUi32s()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp115 /// This function sets all caller-saved registers in Defs.
118 /// This function sets all unallocatable registers in Defs.
136 BitVector Defs, Uses; member in __anon24727::RegDefsUses
192 /// Update Defs and Uses. Return true if there exist dependences that
194 /// Defs.
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon24727::MemDefsUses
346 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
352 // If MI is a call, add RA to Defs to prevent users of RA from going into in init()
355 Defs.set(Mips::RA); in init()
361 Defs in init()
[all...]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ExecutionEngine/Orc/
H A DCompileOnDemandLayer.cpp244 IRMaterializationUnit::SymbolNameToDefinitionMap Defs) { in emitPartition()
254 assert(Defs.count(Name) && "No definition for symbol"); in emitPartition()
255 RequestedGVs.insert(Defs[Name]); in emitPartition()
267 Defs.clear(); in emitPartition()
275 std::move(TSM), R.getSymbols(), std::move(Defs), *this)); in emitPartition()
242 emitPartition( MaterializationResponsibility R, ThreadSafeModule TSM, IRMaterializationUnit::SymbolNameToDefinitionMap Defs) emitPartition() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DLiveVariables.h159 SmallVectorImpl<unsigned> &Defs);
160 void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
178 void runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/
H A DInstruction.h405 SmallVector<WriteState, 4> Defs; member in llvm::mca::InstructionBase
414 SmallVectorImpl<WriteState> &getDefs() { return Defs; } in getDefs()
415 const ArrayRef<WriteState> getDefs() const { return Defs; } in getDefs()
424 return any_of(Defs, in hasDependentUsers()
430 for (const WriteState &Def : Defs) in getNumUsers()

Completed in 29 milliseconds

123