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Searched refs:Dd (Results 1 - 7 of 7) sorted by relevance

/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc1407 // vcvt: Dd = Sm
1409 // vcvt.f64.s32 Dd, Dd, #<fbits>
1410 // Dd = vabs(Dm)
1412 // Dd = vneg(Dm)
1414 // Dd = vadd(Dn, Dm)
1416 // Dd = vsub(Dn, Dm)
1418 // Dd = vmul(Dn, Dm)
1420 // Dd = vmla(Dn, Dm)
1422 // Dd
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/third_party/ffmpeg/libavcodec/
H A Dvp3dsp.c55 int A, B, C, D, Ad, Bd, Cd, Dd, E, F, G, H; in idct() local
74 Dd = B + D; in idct()
98 ip[3 * 8] = Ed + Dd; in idct()
99 ip[4 * 8] = Ed - Dd; in idct()
123 Dd = B + D; in idct()
153 dst[3 * stride] = av_clip_uint8((Ed + Dd) >> 4); in idct()
154 dst[4 * stride] = av_clip_uint8((Ed - Dd) >> 4); in idct()
165 dst[3 * stride] = av_clip_uint8(dst[3 * stride] + ((Ed + Dd) >> 4)); in idct()
166 dst[4 * stride] = av_clip_uint8(dst[4 * stride] + ((Ed - Dd) >> 4)); in idct()
206 int A, B, C, D, Ad, Bd, Cd, Dd, in idct10() local
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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.cpp1201 void AssemblerARM32::emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn,
1205 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
1206 (getXXXXInRegYXXXX(Dd) << 12) | (IsFloatTy ? B10 : 0) |
1212 void AssemblerARM32::emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd,
1217 emitSIMDBase(Opcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,
1270 IValueT Dd, IValueT Dn, IValueT Dm) {
1271 assert(Dd < RegARM32::getNumDRegs());
1278 (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
1279 (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
1287 IValueT Dd
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H A DIceAssemblerARM32.h475 // Dd = Dm
778 // Pattern cccc111xxDxxxxxxdddd101xxxMxmmmm where cccc=Cond, Ddddd=Dd,
780 void emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Sm);
782 // Pattern 111100000D00nnnnddddttttssaammmm | Opcode where Ddddd=Dd, nnnn=Rn,
785 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
789 // Pattern 111100000D00nnnnddddss00aaaammmm | Opcode where Ddddd=Dd, nnnn=Rn,
791 void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
830 // 111100100D00nnnndddn00F0NQM0mmmm where Dddd=Dd, Nnnn=Dn, Mmmm=Dm,
832 void emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn, IValueT Dm,
837 void emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, IValue
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/third_party/ffmpeg/libavcodec/mips/
H A Dvp3dsp_idct_msa.c31 v4i32 A, B, C, D, Ad, Bd, Cd, Dd, E, F, G, H; in idct_msa() local
86 Dd = B + D; in idct_msa()
101 r3_r = Ed + Dd; in idct_msa()
102 r4_r = Ed - Dd; in idct_msa()
114 Dd = B + D; in idct_msa()
129 r3_l = Ed + Dd; in idct_msa()
130 r4_l = Ed - Dd; in idct_msa()
146 Dd = B + D; in idct_msa()
167 E = (Ed + Dd) >> 4; in idct_msa()
168 F = (Ed - Dd) >> in idct_msa()
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H A Dvp3dsp_idct_mmi.c114 "paddh %[Dd], %[B], %[D] \n\t" in idct_row_mmi()
158 "paddh %[ftmp3], %[Ed], %[Dd] \n\t" in idct_row_mmi()
159 "psubh %[ftmp4], %[Ed], %[Dd] \n\t" in idct_row_mmi()
181 [Cd]"=&f"(ftmp[18]), [Dd]"=&f"(ftmp[19]), [Ed]"=&f"(ftmp[20]), in idct_row_mmi()
276 "paddh %[Dd], %[B], %[D] \n\t" in idct_column_true_mmi()
336 "paddh %[ftmp3], %[Ed], %[Dd] \n\t" in idct_column_true_mmi()
338 "psubh %[ftmp4], %[Ed], %[Dd] \n\t" in idct_column_true_mmi()
400 [Cd]"=&f"(ftmp[18]), [Dd]"=&f"(ftmp[19]), [Ed]"=&f"(ftmp[20]), in idct_column_true_mmi()
495 "paddh %[Dd], %[B], %[D] \n\t" in idct_column_false_mmi()
554 "paddh %[ftmp3], %[Ed], %[Dd] \ in idct_column_false_mmi()
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/third_party/ffmpeg/libavcodec/ppc/
H A Dvp3dsp_altivec.c45 vec_s16 A, B, C, D, Ad, Bd, Cd, Dd, E, F, G, H;\
90 Dd = vec_add(B, D);\
113 b3 = SHIFT(vec_add(Ed, Dd));\
114 b4 = SHIFT(vec_sub(Ed, Dd));\

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