Searched refs:DMULT (Results 1 - 7 of 7) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 435 DMULT = 4, enumerator
592 int latency = Latency::DMULT + Latency::MOVF_LOW; in Mul64Latency()
616 int latency = Latency::DMULT + Latency::MOVF_HIGH; in Mulh64Latency()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 428 DMULT = 4, enumerator
595 latency = Latency::DMULT + Latency::MFLO; in DmulLatency()
634 latency = Latency::DMULT + Latency::MFHI; in DMulhLatency()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 199 #define DMULT (HI(0) | LO(28)) macro
1842 FAIL_IF(push_inst(compiler, DMULT | S(src1) | T(src2), MOVABLE_INS)); in emit_single_op()
1846 FAIL_IF(push_inst(compiler, SELECT_OP(DMULT, MULT) | S(src1) | T(src2), MOVABLE_INS)); in emit_single_op()
1855 FAIL_IF(push_inst(compiler, SELECT_OP(DMULT, MULT) | S(src1) | T(src2), MOVABLE_INS)); in emit_single_op()
2179 FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? DMULTU : DMULT) | S(SLJIT_R0) | T(SLJIT_R1), MOVABLE_INS)); in sljit_emit_op0()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 537 DMULT = ((3U << 3) + 4),
1342 FunctionFieldToBitNumber(MULT) | FunctionFieldToBitNumber(DMULT) |
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| H A D | assembler-mips64.cc | 1825 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DMULT); in dmult()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 5059 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT, in expandMulImm()
5079 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT, in expandMulO()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3952 case DMULT: // DMULT == D_MUL_MUH. in DecodeTypeRegisterSPECIAL()
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