Searched refs:DMUL (Results 1 - 6 of 6) sorted by relevance
| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_opcode_tmp.h | 201 OP12(DMUL)
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 432 DMUL = 7, enumerator
593 latency = Latency::DMUL; in DmulLatency()
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| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_target_gv100.cpp | 145 OPINFO(DMUL , R , NA , RIC , NA , NONE, NONE);
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| H A D | nv50_ir_from_tgsi.cpp | 837 NV50_IR_OPCODE_CASE(DMUL, MUL); in translateOpcode()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeMIPS_common.c | 192 #define DMUL (HI(0) | (2 << 6) | LO(28)) macro
1835 return push_inst(compiler, SELECT_OP(DMUL, MUL) | S(src1) | T(src2) | D(dst), DR(dst)); in emit_single_op()
1852 FAIL_IF(push_inst(compiler, SELECT_OP(DMUL, MUL) | S(src1) | T(src2) | D(dst), DR(dst))); in emit_single_op()
2169 FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? DMULU : DMUL) | S(SLJIT_R0) | T(SLJIT_R1) | D(TMP_REG3), DR(TMP_REG3))); in sljit_emit_op0()
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| /third_party/node/deps/v8/src/codegen/ppc/ |
| H A D | constants-ppc.h | 1399 V(dmul, DMUL, 0xEC000044) \
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