Searched refs:DIV_D (Results 1 - 12 of 12) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 533 DIV_D = 32, enumerator
1324 return Latency::DIV_D; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | constants-loong64.h | 369 DIV_D = 0x44U << 15,
1106 case DIV_D:
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| H A D | assembler-loong64.cc | 1194 GenRegister(DIV_D, rk, rj, rd); in div_d()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 532 DIV_D = 32, enumerator
1520 return Latency::DIV_D; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 503 DIV_D = 32, enumerator
1796 return Latency::DIV_D; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 685 DIV_D = ((0U << 3) + 3),
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| H A D | assembler-mips64.cc | 2876 GenInstrRegister(COP1, S, ft, fs, fd, DIV_D); in div_s()
2880 GenInstrRegister(COP1, D, ft, fs, fd, DIV_D); in div_d()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 640 DIV_D = ((0U << 3) + 3),
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| H A D | assembler-mips.cc | 2605 GenInstrRegister(COP1, D, ft, fs, fd, DIV_D); in div_d()
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| /third_party/node/deps/v8/src/execution/loong64/ |
| H A D | simulator-loong64.cc | 3702 case DIV_D: {
3703 printf_instr("DIV_D\t %s: %016lx, %s, %016lx, %s, %016lx\n",
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 3193 case DIV_D: in DecodeTypeRegisterDRsType()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 2812 case DIV_D: in DecodeTypeRegisterDRsType()
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