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Searched refs:CP_REG (Results 1 - 7 of 7) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dfd2_emit.c221 OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL)); in fd2_emit_state_binning()
225 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK)); in fd2_emit_state_binning()
230 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL)); in fd2_emit_state_binning()
251 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK)); in fd2_emit_state()
263 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL)); in fd2_emit_state()
267 OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF)); in fd2_emit_state()
279 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL)); in fd2_emit_state()
285 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE)); in fd2_emit_state()
292 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL)); in fd2_emit_state()
304 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCAL in fd2_emit_state()
[all...]
H A Dfd2_draw.c85 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
118 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
147 OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
236 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
246 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
263 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
271 OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
282 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG));
287 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
291 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MAS
[all...]
H A Dfd2_gmem.c105 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO)); in emit_gmem2mem_surf()
110 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL)); in emit_gmem2mem_surf()
126 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX)); in emit_gmem2mem_surf()
155 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
159 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
164 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
171 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
175 OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
179 OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
187 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_T
[all...]
H A Dfd2_program.c264 OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC)); in fd2_program_emit()
272 OUT_RING(ring, CP_REG(REG_A2XX_SQ_PROGRAM_CNTL)); in fd2_program_emit()
/third_party/mesa3d/src/gallium/drivers/freedreno/a3xx/
H A Dfd3_query.c56 OUT_RING(ring, CP_REG(REG_A3XX_RB_SAMPLE_COUNT_ADDR) | 0x80000000); in occlusion_get_sample()
/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_query.c62 OUT_RING(ring, CP_REG(REG_A4XX_RB_SAMPLE_COUNT_CONTROL) | 0x80000000); in occlusion_get_sample()
/third_party/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_util.h230 #define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000)))) macro

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