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Searched refs:CPSR (Results 1 - 25 of 26) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp74 // 2 - Always set CPSR.
217 // Last instruction to define CPSR in the current block.
219 // Was CPSR last defined by a high latency instruction?
220 // When CPSRDef is null, this refers to CPSR defs in predecessors.
256 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
272 /// the 's' 16-bit instruction partially update CPSR. Abort the
273 /// transformation to avoid adding false dependency on last CPSR setting
277 /// last instruction that defines the CPSR and the current instruction. If there
279 /// before the CPSR setting instruction anyway.
304 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
[all...]
H A DARMLowOverheadLoops.cpp698 MIB.addReg(ARM::CPSR); in RevertWhile()
707 // If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS. in RevertLoopDec()
709 (RDA->isRegUsedAfter(MI, ARM::CPSR) || in RevertLoopDec()
710 !RDA->hasSameReachingDef(MI, &MBB->back(), ARM::CPSR))) in RevertLoopDec()
722 MIB.addReg(ARM::CPSR); in RevertLoopDec()
755 MIB.addReg(ARM::CPSR); in RevertLoopEnd()
844 // Bail if we define CPSR and it is not dead in RemoveLoopUpdate()
845 if (!Def->registerDefIsDead(ARM::CPSR, TRI)) { in RemoveLoopUpdate()
846 LLVM_DEBUG(dbgs() << "ARM Loops: CPSR is not dead\n"); in RemoveLoopUpdate()
H A DThumb1InstrInfo.cpp59 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
63 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
144 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR in canCopyGluedNodeDuringSchedule()
H A DARMFastISel.cpp238 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
249 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
250 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { in DefinesOptionalPredicate() argument
254 // Look to see if our OptionalDef is defining CPSR or CCR. in DefinesOptionalPredicate()
257 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
258 *CPSR = true; in DefinesOptionalPredicate()
281 // CPSR defs that need to be added before the remaining operands. See s_cc_out
294 // defines CPSR. All other OptionalDefines in ARM are the CCR register. in AddOptionalDefs()
295 bool CPSR in AddOptionalDefs() local
[all...]
H A DARMBaseInstrInfo.cpp447 // For conditional branches, we use addOperand to preserve CPSR flags. in insertBranch()
550 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) || in DefinesPredicate()
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) { in DefinesPredicate()
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
687 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
692 // all definitions of CPSR are dead in IsCPSRDead()
785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
805 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
923 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
926 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
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H A DThumb2ITBlockPass.cpp155 // If the CPSR is defined by this copy, then we don't want to move it. E.g., in MoveCopyOutOfITBlock()
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
H A DARMAsmPrinter.cpp1680 .addReg(ARM::CPSR)
1736 .addReg(ARM::CPSR)
1867 .addReg(ARM::CPSR)
1886 .addReg(ARM::CPSR)
1901 .addReg(ARM::CPSR)
H A DARMInstructionSelector.cpp604 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
798 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1156 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
H A DARMExpandPseudoInsts.cpp983 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1006 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1104 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1126 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1391 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
1582 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
H A DThumb1FrameLowering.cpp417 .addDef(ARM::CPSR) in emitPrologue()
423 .addDef(ARM::CPSR) in emitPrologue()
H A DARMISelLowering.cpp3136 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be in LowerGlobalTLSAddressDarwin()
4317 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR, in getARMCmp()
4474 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO()
4594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT()
5046 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5081 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5188 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
5237 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND()
5291 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5300 SDValue CCR = DAG.getRegister(ARM::CPSR, MV in LowerBR_CC()
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H A DARMBaseInstrInfo.h166 // CPSR defined in instruction
478 /// This operand will always refer to CPSR and it will have the Define flag set.
481 return MachineOperand::CreateReg(ARM::CPSR, in t1CondCodeOp()
676 /// CPSR def operand.
H A DThumb2InstrInfo.cpp496 !MI.definesRegister(ARM::CPSR)) {
H A DARMLoadStoreOptimizer.cpp207 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
208 // If the instruction has live CPSR def, then it's not safe to fold it in definesCPSR()
520 // SUBS/ADDS using this register, with a dead def of the CPSR. in UpdateBaseRegUses()
543 // after an instruction that has a live CPSR def. in UpdateBaseRegUses()
632 // For Thumb1 targets, it might be necessary to clobber the CPSR to merge. in CreateLoadStoreMulti()
635 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) == in CreateLoadStoreMulti()
675 // clobbering the CPSR (i.e. not using ADDS/SUBS). in CreateLoadStoreMulti()
1184 /// return the amount it is incremented/decremented. Returns 0 if the CPSR flags
H A DARMISelDAGToDAG.cpp108 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
3070 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), Src, in SelectCMPZ()
3326 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), in Select()
3612 SDValue Ops[] = {CurDAG->getRegister(ARM::CPSR, MVT::i32), X, in Select()
H A DARMConstantIslandPass.cpp1866 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout in optimizeThumb2Branches()
1868 if (!Br.MI->killsRegister(ARM::CPSR)) in optimizeThumb2Branches()
H A DARMFrameLowering.cpp2461 .addReg(ARM::CPSR); in adjustForSegmentedStacks()
/third_party/node/deps/v8/src/codegen/arm/
H A Dconstants-arm.h224 enum SRegister { CPSR = 0 << 22, SPSR = 1 << 22 }; enumerator
243 CPSR_c = CPSR | 1 << 16,
244 CPSR_x = CPSR | 1 << 17,
245 CPSR_s = CPSR | 1 << 18,
246 CPSR_f = CPSR | 1 << 19,
H A Dassembler-arm.cc2065 DCHECK(((fields & 0xFFF0FFFF) == CPSR) || ((fields & 0xFFF0FFFF) == SPSR)); in msr()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2345 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
4960 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" in parseMSRMaskOperand()
6886 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
9523 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
9573 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
9580 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
9626 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
9634 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
9832 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
10000 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) in processInstruction()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp309 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or in getCCOutOpValue()
311 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
730 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { in HasConditionalBranch()
H A DARMInstPrinter.cpp930 O << "CPSR";
999 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1000 "Expect ARM CPSR register!");
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp901 case Sparc::CPSR: in parseSparcAsmOperand()
1049 RegNo = Sparc::CPSR; in matchRegisterName()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp727 // implicitly set CPSR. Since it's not represented in the encoding, the
728 // auto-generated decoder won't inject the CPSR operand. We need to fix
738 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
743 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
839 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
901 I->setReg(ARM::CPSR); in UpdateThumbVFPPredicate()
1436 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodePredicateOperand()
1443 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); in DecodeCCOutOperand()
/third_party/vixl/src/aarch32/
H A Dinstructions-aarch32.h773 enum SpecialRegisterType { APSR = 0, CPSR = 0, SPSR = 1 };

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