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Searched refs:CIK_UCONFIG_REG_OFFSET (Results 1 - 9 of 9) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h145 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
149 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()
155 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq_perfctr()
159 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq_perfctr()
173 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
183 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
191 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_perfctr_reg()
203 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_perfctr_reg()
210 assert(reg < CIK_UCONFIG_REG_OFFSET); in radeon_set_privileged_config_reg()
H A Dradv_device_generated_commands.c840 &b, (R_03090C_VGT_INDEX_TYPE - CIK_UCONFIG_REG_OFFSET) >> 2 | (2u << 28)); in build_dgc_prepare_shader()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h183 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
186 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()
199 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
202 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
H A Dr600d_common.h33 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h139 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
141 radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2); \
156 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
163 radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2 | ((idx) << 28)); \
286 assert((reg) < CIK_UCONFIG_REG_OFFSET); \
H A Dsi_pm4.c95 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) { in si_pm4_set_reg()
97 reg -= CIK_UCONFIG_REG_OFFSET; in si_pm4_set_reg()
H A Dsi_cp_reg_shadowing.c44 offset = CIK_UCONFIG_REG_OFFSET; in si_build_load_reg()
/third_party/mesa3d/src/amd/common/
H A Dsid.h36 #define CIK_UCONFIG_REG_OFFSET 0x00030000 macro
44 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
H A Dac_debug.c293 ac_parse_set_reg_packet(f, count, CIK_UCONFIG_REG_OFFSET, ib); in ac_parse_packet3()

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