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Searched refs:CIK_UCONFIG_REG_END (Results 1 - 6 of 6) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h145 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
155 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq_perfctr()
173 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
191 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_perfctr_reg()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_cs.h183 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_seq()
199 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); in radeon_set_uconfig_reg_idx()
H A Dr600d_common.h34 #define CIK_UCONFIG_REG_END 0x00038000 macro
/third_party/mesa3d/src/amd/common/
H A Dsid.h37 #define CIK_UCONFIG_REG_END 0x00040000 macro
44 #define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_pm4.c95 } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) { in si_pm4_set_reg()
H A Dsi_build_pm4.h139 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
156 assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \

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