Searched refs:CEIL_W_S (Results 1 - 9 of 9) sorted by relevance
| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | instruction-scheduler-riscv64.cc | 483 CEIL_W_S = 4, enumerator
1391 return Latency::CEIL_W_S + Latency::MOVF_FREG; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | instruction-scheduler-mips64.cc | 482 CEIL_W_S = 4, enumerator
1587 return Latency::CEIL_W_S + Latency::MFC1; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | instruction-scheduler-mips.cc | 453 CEIL_W_S = 4, enumerator
1784 return Latency::CEIL_W_S; in GetInstructionLatency()
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| /third_party/node/deps/v8/src/codegen/mips64/ |
| H A D | constants-mips64.h | 670 CEIL_W_S = ((1U << 3) + 6),
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| H A D | assembler-mips64.cc | 2965 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S); in ceil_w_s()
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| /third_party/node/deps/v8/src/codegen/mips/ |
| H A D | constants-mips.h | 624 CEIL_W_S = ((1U << 3) + 6),
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| H A D | assembler-mips.cc | 2695 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S); in ceil_w_s()
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| /third_party/node/deps/v8/src/execution/mips64/ |
| H A D | simulator-mips64.cc | 2978 case CEIL_W_S: // Round double to word towards positive infinity. in DecodeTypeRegisterSRsType()
3058 // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented. in DecodeTypeRegisterSRsType()
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| /third_party/node/deps/v8/src/execution/mips/ |
| H A D | simulator-mips.cc | 3499 case CEIL_W_S: // Round double to word towards positive infinity. in DecodeTypeRegisterSRsType()
3564 // CEIL_W_S CEIL_L_S CVT_PS_S are unimplemented. in DecodeTypeRegisterSRsType()
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