| /third_party/node/deps/v8/src/builtins/arm64/ |
| H A D | builtins-arm64.cc | 119 __ Bic(slot_count, slot_count_without_rounding, 1); in Generate_JSBuiltinsConstructStubHelper()
318 __ Bic(x10, x12, 1); in Generate_JSConstructStubGeneric()
518 __ Bic(x11, x11, 1); in Generate_ResumeGeneratorTrampoline()
890 __ Bic(slots_to_claim, slots_to_claim, 1); in Generate_JSEntryTrampolineHelper()
1515 __ Bic(x11, x11, 1); in Generate_InterpreterEntryTrampoline()
1674 __ Bic(slots_to_claim, slots_to_claim, 1); in GenerateInterpreterPushArgs()
2717 __ Bic(slots_to_claim, slots_to_claim, 1); in Generate_PushBoundArguments()
3981 __ Bic(unwind_limit, unwind_limit, 1); in Generate_DeoptimizationEntry()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-assembler-aarch32.cc | 961 __ Bic(r3, r0, r1); in TEST()
962 __ Bic(r4, r0, Operand(r1, LSL, 4)); in TEST()
963 __ Bic(r5, r0, Operand(r1, LSR, 1)); in TEST()
964 __ Bic(r6, r0, Operand(r1, ASR, 20)); in TEST()
965 __ Bic(r7, r0, Operand(r1, ROR, 28)); in TEST()
966 __ Bic(r8, r0, 0x1f); in TEST()
970 __ Bic(r9, r1, Operand(r1, RRX)); in TEST()
974 __ Bic(r10, r1, Operand(r1, RRX)); in TEST()
3267 __ Bic(r0, r0, 0); in TEST()
3311 __ Bic(r in TEST()
[all...] |
| H A D | test-disasm-a32.cc | 1492 COMPARE_BOTH(Bic(r0, r1, 0xffffffff), "mov r0, #0\n"); in TEST()
1493 COMPARE_BOTH(Bic(r0, r0, 0), ""); in TEST()
3293 COMPARE_T32(Bic(eq, r7, r7, r6), in TEST()
3297 COMPARE_T32(Bic(eq, r8, r8, r6), in TEST()
4048 CHECK_T32_16(Bic(DontCare, r7, r7, r6), "bics r7, r6\n"); in TEST()
4050 CHECK_T32_16_IT_BLOCK(Bic(DontCare, eq, r7, r7, r6), in TEST()
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| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 122 M(Bic) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 122 M(Bic) \
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| H A D | test-simulator-cond-rd-rn-operand-const-a32.cc | 122 M(Bic) \
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| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 122 M(Bic) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 122 M(Bic) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 122 M(Bic) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 122 M(Bic) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 122 M(Bic) \
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 360 V(bic, Bic) \
492 void Bic(const VRegister& vd, const int imm8, const int left_shift = 0) { in Bic() function in v8::internal::TurboAssembler
684 inline void Bic(const Register& rd, const Register& rn,
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| H A D | macro-assembler-arm64-inl.h | 43 void TurboAssembler::Bic(const Register& rd, const Register& rn, in Bic() function in v8::internal::TurboAssembler
1340 Bic(tmp, tmp, 1); in DropArguments()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 757 __ Bic(x2, x0, Operand(x1)); in TEST()
758 __ Bic(w3, w0, Operand(w1, LSL, 4)); in TEST()
759 __ Bic(x4, x0, Operand(x1, LSL, 4)); in TEST()
760 __ Bic(x5, x0, Operand(x1, LSR, 1)); in TEST()
761 __ Bic(w6, w0, Operand(w1, ASR, 20)); in TEST()
762 __ Bic(x7, x0, Operand(x1, ASR, 20)); in TEST()
763 __ Bic(w8, w0, Operand(w1, ROR, 28)); in TEST()
764 __ Bic(x9, x0, Operand(x1, ROR, 24)); in TEST()
765 __ Bic(x10, x0, Operand(0x1f)); in TEST()
766 __ Bic(x1 in TEST()
[all...] |
| H A D | test-disasm-neon-aarch64.cc | 1757 COMPARE_MACRO(Bic(v6.V8B(), v7.V8B(), v8.V8B()), "bic v6.8b, v7.8b, v8.8b"); in TEST()
1758 COMPARE_MACRO(Bic(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
3160 COMPARE_MACRO(Bic(v4.V4H(), 0xaa, 0), "bic v4.4h, #0xaa, lsl #0"); in TEST()
3161 COMPARE_MACRO(Bic(v1.V8H(), 0xcc, 8), "bic v1.8h, #0xcc, lsl #8"); in TEST()
3162 COMPARE_MACRO(Bic(v4.V2S(), 0xaa, 0), "bic v4.2s, #0xaa, lsl #0"); in TEST()
3163 COMPARE_MACRO(Bic(v1.V2S(), 0xcc, 8), "bic v1.2s, #0xcc, lsl #8"); in TEST()
3164 COMPARE_MACRO(Bic(v4.V4S(), 0xaa, 16), "bic v4.4s, #0xaa, lsl #16"); in TEST()
3165 COMPARE_MACRO(Bic(v1.V4S(), 0xcc, 24), "bic v1.4s, #0xcc, lsl #24"); in TEST()
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| H A D | test-assembler-neon-aarch64.cc | 6048 __ Bic(v16.V16B(), v0.V16B(), v0.V16B()); // self test in TEST()
6049 __ Bic(v17.V16B(), v0.V16B(), v1.V16B()); // all combinations in TEST()
6050 __ Bic(v24.V8B(), v0.V8B(), v0.V8B()); // self test in TEST()
6051 __ Bic(v25.V8B(), v0.V8B(), v1.V8B()); // all combinations in TEST()
7365 __ Bic(v16.V4H(), 0x00, 0); in TEST()
7366 __ Bic(v17.V4H(), 0xff, 8); in TEST()
7367 __ Bic(v18.V8H(), 0x00, 0); in TEST()
7368 __ Bic(v19.V8H(), 0xff, 8); in TEST()
7370 __ Bic(v20.V2S(), 0x00, 0); in TEST()
7371 __ Bic(v2 in TEST()
[all...] |
| H A D | test-disasm-aarch64.cc | 2910 COMPARE_MACRO(Bic(w6, w7, 0), "mov w6, w7"); in TEST()
2911 COMPARE_MACRO(Bic(x6, x7, 0), "mov x6, x7"); in TEST()
2927 COMPARE_MACRO(Bic(w18, w19, 0xffffffff), "mov w18, #0x0"); in TEST()
2928 COMPARE_MACRO(Bic(x18, x19, 0xffffffff), "and x18, x19, #0xffffffff00000000"); in TEST()
2929 COMPARE_MACRO(Bic(x18, x19, 0xffffffffffffffff), "mov x18, #0x0"); in TEST()
2957 COMPARE_MACRO(Bic(x0, x0, 0x4242), in TEST()
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| H A D | test-disasm-sve-aarch64.cc | 2381 COMPARE_MACRO(Bic(z17.VnB(), p7.Merging(), z17.VnB(), z10.VnB()), in TEST()
2383 COMPARE_MACRO(Bic(z17.VnS(), p7.Merging(), z10.VnS(), z17.VnS()), in TEST()
2387 COMPARE_MACRO(Bic(z17.VnD(), p7.Merging(), z7.VnD(), z27.VnD()), in TEST()
5981 COMPARE_MACRO(Bic(z11, z2, z16), "bic z11.d, z2.d, z16.d"); in TEST()
5986 COMPARE_MACRO(Bic(z11.VnS(), z2.VnS(), z16.VnS()), "bic z11.d, z2.d, z16.d"); in TEST()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 384 Bic, enumerator
1006 using InstARM32Bic = InstARM32ThreeAddrGPR<InstARM32::Bic>;
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| H A D | IceInstARM32.cpp | 3409 template class InstARM32ThreeAddrGPR<InstARM32::Bic>;
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 793 void Bic(const Register& rd, const Register& rn, const Operand& operand);
2855 V(bic, Bic) \
3261 void Bic(const VRegister& vd, const int imm8, const int left_shift = 0) { in Bic() function in vixl::aarch64::MacroAssembler
3738 void Bic(const ZRegister& zd,
3742 void Bic(const PRegisterWithLaneSize& pd, in Bic() function in vixl::aarch64::MacroAssembler
3750 void Bic(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Bic() function in vixl::aarch64::MacroAssembler
3756 void Bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm) { in Bic() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.cc | 822 void MacroAssembler::Bic(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
2783 Bic(sp, StackPointer(), 0xf); in Emit()
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| H A D | macro-assembler-sve-aarch64.cc | 630 V(Bic, bic) \
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 1523 void Bic(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1551 void Bic(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1552 Bic(al, rd, rn, operand); in MacroAssembler()
1554 void Bic(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
1561 Bic(cond, rd, rn, operand); in MacroAssembler()
1573 Bic(cond, rd, rn, operand); in MacroAssembler()
1578 void Bic(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
1582 Bic(flags, al, rd, rn, operand); in MacroAssembler()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1160 __ Bic(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction()
1164 __ Bic(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction()
2660 SIMD_BINOP_CASE(kArm64S128AndNot, Bic, 16B); in AssembleArchInstruction()
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