/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
H A D | SystemZLongBranch.cpp | 345 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { in setWorstCaseAddresses() 446 for (unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) { in relaxBranches()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
H A D | SwitchLoweringUtils.cpp | 436 BitTestInfo BTI; in buildBitTests() local 449 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraProb)); in buildBitTests() 453 ContiguousRange, nullptr, nullptr, std::move(BTI), in buildBitTests()
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/third_party/skia/third_party/externals/sfntly/java/src/com/google/typography/font/sfntly/table/opentype/ |
H A D | LanguageTag.java | 61 BTI("Beti", "btb"), enum constant
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/third_party/node/deps/v8/src/codegen/arm64/ |
H A D | instructions-arm64.h | 390 case BTI: in IsBti()
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H A D | constants-arm64.h | 389 BTI = 32, enumerator 395 // In a guarded page, only BTI and PACI[AB]SP instructions are allowed to be 399 // Do not emit a BTI instruction. 402 // Emit a BTI instruction. Cannot be the target of indirect jumps/calls. 405 // Emit a "BTI c" instruction. Can be the target of indirect jumps (BR) with 409 // Emit a "BTI j" instruction. Can be the target of indirect jumps (BR). 412 // Emit a "BTI jc" instruction, which is a combination of "BTI j" and "BTI c". 415 // Emit a PACIBSP instruction, which acts like a "BTI [all...] |
H A D | assembler-arm64.cc | 1201 op = BTI; in bti() 1214 // We always want to generate a BTI instruction here, so disallow in bti()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.cpp | 1142 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop); in printBTIHintOp() local 1143 if (BTI) in printBTIHintOp() 1144 O << BTI->Name; in printBTIHintOp()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 441 struct BTI : SysAlias { struct
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/third_party/vixl/src/aarch64/ |
H A D | instructions-aarch64.h | 509 case BTI: in IsBti()
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H A D | cpu-features-auditor-aarch64.cc | 1294 case BTI: in VisitSystem()
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H A D | constants-aarch64.h | 389 BTI = 32, enumerator 397 EmitBTI = BTI,
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H A D | simulator-aarch64.cc | 639 // BTI state. in Simulator() 6787 case BTI: in Simulator() 6789 VIXL_ABORT_WITH_MSG("Executing BTI with wrong BType."); in Simulator() 6795 VIXL_ABORT_WITH_MSG("Executing BTI c with wrong BType."); in Simulator() 6800 VIXL_ABORT_WITH_MSG("Executing BTI j with wrong BType."); in Simulator()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 2436 /// tryParseBTIHint - Try to parse a BTI operand, mapped to Hint command 2447 auto BTI = AArch64BTIHint::lookupBTIByName(Tok.getString()); in tryParseBTIHint() local 2448 if (!BTI) { in tryParseBTIHint() 2455 BTI->Encoding, Tok.getString(), S, getContext())); in tryParseBTIHint()
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/third_party/node/deps/v8/src/diagnostics/arm64/ |
H A D | disasm-arm64.cc | 1498 case BTI: in VisitSystem()
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/third_party/node/deps/v8/src/execution/arm64/ |
H A D | simulator-arm64.h | 780 // Branch Target Identification (BTI) 785 // * it is a BTI or PACI[AB]SP instruction that accepts the current value of 791 // | | BTYPE to | BTI | BTI j | BTI c | BTI jc | 806 // PACI[AB]SP is treated either like "BTI c" or "BTI jc", according to the 844 // here to be set. This makes PACI[AB]SP behave like "BTI c", in CheckBTypeForPAuth() 861 case BTI in CheckBTypeForBti() [all...] |
H A D | simulator-arm64.cc | 3390 case BTI:
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 6688 auto &BTI = getBackedgeTakenInfo(L); 6689 if (BTI.hasFullInfo()) 6690 return BTI;
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/third_party/vixl/test/aarch64/ |
H A D | test-disasm-aarch64.cc | 3142 COMPARE(hint(BTI), "bti"); in TEST() 3900 // ARMv8.5 - BTI in TEST()
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